TH72016KLD-CAA-000-TU

TH72016
433MHz
FSK/ASK Transmitter
39010 72016 Page 4 of 15 Data Sheet
Rev. 009 Jan/12
f
min
f
c
f
f
max
eff
CL
eff
CL
R1
C1
C0
L1
XTAL
CLCX1 CRO
CX1+CRO
(CX1+CX2) CRO
CX1+CX2+CRO
2.2 FSK Modulation
FSK modulation can be achieved by pulling the
crystal oscillator frequency. A CMOS-
compatible data stream applied at the pin
FSKDTA digitally modulates the XOSC via an
integrated NMOS switch. Two external pulling
capacitors CX1 and CX2 allow the FSK devia-
tion f and the center frequency f
c
to be ad-
justed independently. At FSKDTA = 0, CX2 is
connected in parallel to CX1 leading to the low-
frequency component of the FSK spectrum
(f
min
); while at FSKDTA = 1, CX2 is deactivated
and the XOSC is set to its high frequency f
max
.
An external reference signal can be directly AC-
coupled to the reference oscillator input pin
ROI. Then the transmitter is used without a
crystal. Now the reference signal sets the car-
rier frequency and may also contain the FSK (or
FM) modulation.
Fig. 2: Crystal pulling circuitry
FSKDTA Description
0
f
min
= f
c
- f (FSK switch is closed)
1
f
max
= f
c
+ f (FSK switch is open)
2.3 Crystal Pulling
A crystal is tuned by the manufacturer to the
required oscillation frequency f
0
at a given load
capacitance CL and within the specified calibra-
tion tolerance. The only way to pull the oscilla-
tion frequency is to vary the effective load ca-
pacitance CL
eff
seen by the crystal.
Figure 3 shows the oscillation frequency of a
crystal as a function of the effective load ca-
pacitance. This capacitance changes in accor-
dance with the logic level of FSKDTA around
the specified load capacitance. The figure illus-
trates the relationship between the external
pulling capacitors and the frequency deviation.
It can also be seen that the pulling sensitivity
increases with the reduction of CL. Therefore,
applications with a high frequency deviation
require a low load capacitance. For narrow
band FSK applications, a higher load capaci-
tance could be chosen in order to reduce the
frequency drift caused by the tolerances of the
chip and the external pulling capacitors.
Fig. 3: Crystal pulling characteristic
For ASK applications CX2 can be omitted. Then CX1 has to be adjusted for center frequency.
CX2
VCC
XTAL
CX1
ROI
FSKSW
VEE
TH72016
433MHz
FSK/ASK Transmitter
39010 72016 Page 5 of 15 Data Sheet
Rev. 009 Jan/12
2.4 ASK Modulation
The TH72016 can be ASK-modulated by applying data directly at pin PSEL. This turns the PA on and off
which leads to an ASK signal at the output.
2.5 Output Power Selection
The transmitter is provided with an output power selection feature. There are four predefined output power
steps and one off-step accessible via the power selection pin PSEL. A digital power step adjustment was
chosen because of its high accuracy and stability. The number of steps and the step sizes as well as the
corresponding power levels are selected to cover a wide spectrum of different applications.
The implementation of the output power control
logic is shown in figure 4. There are two
matched current sources with an amount of
about 8 µA. One current source is directly ap-
plied to the PSEL pin. The other current source
is used for the generation of reference voltages
with a resistor ladder. These reference voltages
are defining the thresholds between the power
steps. The four comparators deliver thermome-
ter-coded control signals depending on the
voltage level at the pin PSEL. In order to have a
certain amount of ripple tolerance in a noisy
environment the comparators are provided with
a little hysteresis of about 20 mV. With these
control signals, weighted current sources of the
power amplifier are switched on or off to set the
desired output power level (Digitally Controlled
Current Source). The LOCK signal and the
output of the low voltage detector are gating
this current source.
Fig. 4: Block diagram of output power control circuitry
There are two ways to select the desired output power step. First by applying a DC voltage at the pin PSEL,
then this voltage directly selects the desired output power step. This kind of power selection can be used if
the transmission power must be changed during operation. For a fixed-power application a resistor can be
used which is connected from the PSEL pin to ground. The voltage drop across this resistor selects the de-
sired output power level. For fixed-power applications at the highest power step this resistor can be omitted.
The pin PSEL is in a high impedance state during the “TX standby” mode.
2.6 Lock Detection
The lock detection circuitry turns on the power amplifier only after PLL lock. This prevents from unwanted
emission of the transmitter if the PLL is unlocked.
2.7 Low Voltage Detection
The supply voltage is sensed by a low voltage detect circuitry. The power amplifier is turned off if the supply
voltage drops below a value of about 1.85 V. This is done in order to prevent unwanted emission of the
transmitter if the supply voltage is too low.
&
&
&
PSEL
&
&
RPS
OUT
TH72016
433MHz
FSK/ASK Transmitter
39010 72016 Page 6 of 15 Data Sheet
Rev. 009 Jan/12
2.8 Mode Control Logic
The mode control logic allows two different
modes of operation as listed in the following
table. The mode control pin EN is pulled-down
internally. This guarantees that the whole circuit
is shut down if this pin is left floating.
EN Mode Description
0 TX standby TX disabled
1
TX active
CKOUT active
TX / CKOUT
enabled
2.9 Clock Output
The clock output CKOUT is CMOS-compatible and can be used to drive a microcontroller. The frequency of
the clock can be changed by the clock divider control signal CKDIV, that can be selected according to the
following table. A capacitor at pin CKOUT can be used to control the clock voltage swing and the spurious
emission.
CKDIV Clock divider ratio Clock frequency / fc=433.92MHz
0 4 3.39MHz
1 16 848kHz
2.10 Timing Diagrams
After enabling the transmitter by the EN signal, the power amplifier remains inactive for the time t
on
, the
transmitter start-up time. The crystal oscillator starts oscillation and the PLL locks to the desired output fre-
quency within the time duration t
on
. After successful PLL lock, the LOCK signal turns on the power amplifier,
and then the RF carrier can be FSK or ASK modulated.
Fig. 5: Timing diagrams for FSK and ASK modulation
RF carrier
low
low
high
high
LOCK
FSKDTA
t
low
high
EN
t
on
EN
low
low
high
high
LOCK
PSEL
t
low
high
t
on

TH72016KLD-CAA-000-TU

Mfr. #:
Manufacturer:
Melexis
Description:
RF Transmitter 433MHz FSK/ASK Transmitter w/ clock O/P
Lifecycle:
New from this manufacturer.
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