ICE3B0565JGXUMA1 Datasheet ICE3B0565JGXUMA1, ICE3B0365JGXUMA1 | P10-P12

CoolSET™-F3

ICE3B0365JG/ICE3B0565JG

Version 2.0 10 14 Nov 2006

3.5 Current Limiting

Figure 8 Current Limiting

There is a cycle by cycle Current Limiting realized by

the Current-Limit comparator C10 to provide an

overcurrent detection. The source current of the

integrated Depl. CoolMOS™ is sensed via an external

sense resistor R

Sense

. By means of R

Sense

the source

current is transformed to a sense voltage V

Sense

which

is fed into the pin CS. If the voltage V

Sense

exceeds the

internal threshold voltage V

csth

the comparator C10

immediately turns off the gate drive by resetting the

PWM Latch FF1. A Propagation Delay Compensation

is added to support the immediate shut down without

delay of the integrated internal CoolMOS™ in case of

Current Limiting. The influence of the AC input voltage

on the maximum output power can thereby be avoided.

To prevent the Current Limiting from distortions caused

by leading edge spikes a Leading Edge Blanking is

integrated in the current sense path for the

comparators C10, C12 and the PWM-OP.

The output of comparator C12 is activated by the Gate

G10 if Active Burst Mode is entered. Once activated the

current limiting is thereby reduced to 0.32V. This

voltage level determines the power level when the

Active Burst Mode is left if there is a higher power

demand.

3.5.1 Leading Edge Blanking

Figure 9 Leading Edge Blanking

Each time when the integrated internal CoolMOS™ is

switched on a leading edge spike is generated due to

the primary-side capacitances and secondary-side

rectifier reverse recovery time. This spike can cause

the gate drive to switch off unintentionally. To avoid a

premature termination of the switching pulse, this spike

is blanked out with a time constant of t

LEB

= 220ns.

During this time, the gate drive will not be switched off.

3.5.2 Propagation Delay Compensation

In case of overcurrent detection, the switch-off of the

integrated internal CoolMOS™ is delayed due to the

propagation delay of the circuit. This delay causes an

overshoot of the peak current I

peak

which depends on

the ratio of dI/dt of the peak current (see Figure 10).

Figure 10 Current Limiting

The overshoot of Signal2 is bigger than of Signal1 due

to the steeper rising waveform. This change in the

slope is depending on the AC input voltage.

Propagation Delay Compensation is integrated to limit

the overshoot dependency on dI/dt of the rising primary

current. That means the propagation delay time

between exceeding the current sense threshold V

csth

and the switch off of the integrated internal CoolMOS™

is compensated over temperature within a wide range.

Current Limiting

C10

C12

0.32V

G10

Propagation-Delay

Compensation

csth

Active Burst

Mode

PWM Latch

FF1

10kΩ

1pF

PWM-OP

Leading

Edge

Blanking

220ns

Sense

csth

LEB

= 220ns

Sense

Limit

Propagation Delay

Overshoot1

peak1

Signal1Signal2

Overshoot2

peak2

CoolSET™-F3

ICE3B0365JG/ICE3B0565JG

Version 2.0 11 14 Nov 2006

Current Limiting is now possible in a very accurate way.

E.g. I

peak

= 0.5A with R

Sense

= 2. Without Propagation

Delay Compensation the current sense threshold is set

to a static voltage level V

csth

=1V. A current ramp of

dI/dt = 0.4A/µs, that means dV

Sense

/dt = 0.8V/µs, and a

propagation delay time of i.e. t

Propagation Delay

=180ns

leads then to an I

peak

overshoot of 14.4%. By means of

propagation delay compensation the overshoot is only

about 2% (see Figure 11).

Figure 11 Overcurrent Shutdown

The Propagation Delay Compensation is realized by

means of a dynamic threshold voltage V

csth

(see Figure

12). In case of a steeper slope the switch off of the

driver is earlier to compensate the delay.

Figure 12 Dynamic Voltage Threshold V

csth

3.6 Control Unit

The Control Unit contains the functions for Active Burst

Mode and Auto Restart Mode. The Active Burst Mode

and the Auto Restart Mode are combined with an

Adjustable Blanking Window which is depending on the

external Soft Start capacitor. By means of this

Adjustable Blanking Window, the IC avoids entering

into these two modes accidentally. Furthermore it also

provides a certain time whereby the overload detection

is delayed. This delay is useful for applications which

normally works with a low current and occasionally

require a short duration of high current.

3.6.1 Adjustable Blanking Window

Figure 13 Adjustable Blanking Window

SoftS

swings between 3.2V and 3.6V after the SMPS is

settled and S2 is on while S3 is off, this is due to the

frequency jittering function that is making use of the

Soft Start pin. If overload occurs V

is exceeding 4.5V.

Auto Restart Mode can’t be entered as the gate G5 is

still blocked by the comparator C3. But after V

has

0,9

0,95

1,05

1,1

1,15

1,2

1,25

1,3

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2

with compensation without compensation

Sense

csth

OSC

Signal1 Signal2

Sense

Propagation Delay

max. Duty Cycle

off time

4.0V

4.5V

1.35V

3.0V

Control Unit

Active

Burst

Mode

Auto

Restart

Mode

SoftS

Frequency

Jitter

CoolSET™-F3

ICE3B0365JG/ICE3B0565JG

Version 2.0 12 14 Nov 2006

exceeded 4.5V the switch S2 is opened and S3 is

closed. The external Soft Start capacitor can now be

charged further by the integrated pull up resistor R

SoftS

via switch S3. The comparator C3 releases the gates

G5 and G6 once V

Softs

has exceeded 4.0V. Therefore

there is no entering of Auto Restart Mode possible

during this charging time of the external capacitor

SoftS

. The same procedure happens to the external

Soft Start capacitor if a low load condition is detected

by comparator C5 when V

is falling below 1.35V.

Only after V

SoftS

has exceeded 4.0V and V

is still

below 1.35V Active Burst Mode is entered.

3.6.2 Active Burst Mode

The controller provides Active Burst Mode for low load

conditions at V

OUT

. Active Burst Mode increases

significantly the efficiency at light load conditions while

supporting a low ripple on V

OUT

and fast response on

load jumps. During Active Burst Mode which is

controlled only by the FB signal the IC is always active

and can therefore immediately response on fast

changes at the FB signal. The Startup Cell is kept

switched off to avoid increased power losses for the

self supply.

Figure 14 Active Burst Mode

The Active Burst Mode is located in the Control Unit.

Figure 14 shows the related components.

3.6.2.1 Entering Active Burst Mode

The FB signal is always observed by the comparator

C5 if the voltage level falls below 1.35V. In that case the

switch S1 and S2 is released which allows the

capacitor C

SoftS

to be charged via S3 starting from the

swinging voltage level between 3.2V and 3.6V in

normal operating mode. If V

SoftS

exceeds 4.0V the

comparator C3 releases the gate G6 to enter the Active

Burst Mode. The time window that is generated by

combining the FB and SoftS signals with gate G6

avoids a sudden entering of the Active Burst Mode due

to large load jumps. This time window can be adjusted

by the external capacitor C

SoftS

After entering Active Burst Mode a burst flag is set and

the internal bias is switched off in order to reduce the

current consumption of the IC down to approx. 500uA.

Also, switch S1 is closed to clamped the Soft Start

voltage to 3.0V. In this Off State Phase the IC is no

longer self supplied so that therefore C

VCC

has to

provide the VCC current (see Figure 15). Furthermore

gate G11 is then released to start the next burst cycle

once V

has 3.0V exceeded.

It has to be ensured by the application that the VCC

remains above the Undervoltage Lockout Level of

10.3V to avoid that the Startup Cell is accidentally

switched on. Otherwise power losses are significantly

increased. The minimum VCC level during Active Burst

Mode is depending on the load conditions and the

application. The lowest VCC level is reached at no load

conditions at V

OUT

3.6.2.2 Working in Active Burst Mode

After entering the Active Burst Mode the FB voltage

rises as V

OUT

starts to decrease due to the inactive

PWM section. Comparator C6a observes the FB signal

if the voltage level 3.6V is exceeded. In that case the

internal circuit is again activated by the internal Bias to

start with switching. As now in Active Burst Mode the

gate G10 is released the current limit is only 0.32V to

reduce the conduction losses and to avoid audible

noise. If the load at V

OUT

is still below the starting level

for the Active Burst Mode the FB signal decreases

down to 3.0V. At this level C6b deactivates again the

internal circuit by switching off the internal Bias. The

gate G11 is released as after entering Active Burst

Mode the burst flag is set. If working in Active Burst

Mode the FB voltage is changing like a saw tooth

between 3.0V and 3.61V (see figure 15).

3.6.2.3 Leaving Active Burst Mode

The FB voltage immediately increases if there is a high

load jump. This is observed by comparator C4. As the

current limit is ca. 32% during Active Burst Mode a

certain load jump is needed that FB can exceed 4.5V.

At this time C4 resets the Active Burst Mode which also

4.0V

4.5V

C6a

3.61V

1.35V

Control Unit

Active

Burst

Mode

3.0V

Internal Bias

SoftS

G10

Current

Limiting

C6b

3.0V

G11

Frequency

Jitter

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ICE3B0565JGXUMA1

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