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LTC4252CIMS-2#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
28
4252b12f
APPLICATIONS INFORMATION
Analog Current Limit and Fast Current Limit
In Figure 17a, when SENSE exceeds V
ACL
, GATE is
regulated by the analog current limit amplifier loop. When
SENSE drops below V
ACL
, GATE is allowed to pull up. In
Figure 17b, when a severe fault occurs, SENSE exceeds
V
FCL
and GATE immediately pulls down until the analog
current amplifier establishes control. If the severe fault
causes V
OUT
to exceed V
DRNCL
, the DRAIN pin is clamped
at V
DRNCL
. I
DRN
flows into the DRAIN pin and is multiplied
by 8. This extra current is added to the TIMER pull-up
current of 230µA. This accelerated TIMER current of
[230µA+8 • I
DRN
] produces a shorter circuit breaker fault
delay. Careful selection of C
T
, R
D
and MOSFET can help
prevent SOA damage in a low impedance
fault condition.
Soft-Start
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 2.2V in about 180µs (or 0V to
1.4V in 230µs for the LTC4252C) at GATE start-up, as
shown in Figure 18a. If a soft-start capacitor, C
SS
, is con-
nected to this SS pin, the soft-start response is modified
from a linear
ramp to an RC response (Equation6), as
shown in Figure 18b. This feature allows load current to
slowly ramp-up at GATE start-up. Soft-start is initiated at
time point 3 by a TIMER transition from V
TMRH
to V
TMRL
(time points 1 to 2) or by the OV pin falling below the
V
OVLO
threshold after an OV condition. When the SS pin
is below 0.2V, the analog
current limit amplifier holds
GATE low. Above 0.2V, GATE is released and 58µA ramps
up the compensation network and GATE capacitance at
time point 4. Meanwhile, the SS pin voltage continues to
ramp up. When GATE reaches the MOSFET’s threshold,
the MOSFET begins to conduct. Due to the MOSFET’s high
g
m
, the MOSFET current quickly reaches the soft-start
control value of V
ACL
(t) (Equation 7). At time point 6, the
GATE voltage is controlled by the current limit amplifier.
The soft-start control voltage reaches the circuit breaker
voltage, V
CB
, at time point 7 and the circuit breaker TIMER
activates. As the load capacitor nears full charge, load
TIMER
GATE
SENSE
V
OUT
V
ACL
V
CB
SS
DRAIN
V
TMRH
230µA + 8 • I
DRN
4252B12 F17
PWRGD
5.8µA
5.8µA
TIMER
GATE
SENSE
V
OUT
V
ACL
V
CB
V
FCL
SS
DRAIN
V
TMRH
V
DRNCL
230µA + 8 • I
DRN
PWRGD
1 21 432
CB TIMES OUT
Figure 17. Current Limit Behavior (All Waveforms Are Referenced to V
EE
)
(17a) Analog Current Limit Fault
(17b) Fast Current Limit Fault
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
29
4252b12f
APPLICATIONS INFORMATION
current begins to decline below V
ACL
(t). The current limit
loop shuts off and GATE releases at time point 8. At time
point9, the SENSE voltage falls below V
CB
and TIMER
deactivates.
Large values of C
SS
can cause premature circuit breaker
time out as V
ACL
(t) may exceed the V
CB
potential during
the circuit breaker delay. The load capacitor is unable to
achieve full
charge in one GATE start-up cycle. A more
serious side effect of large C
SS
values is SOA duration
may be exceeded during soft-start into a low impedance
load. A soft-start voltage below V
CB
will not activate the
circuit breaker TIMER.
Power Limit Circuit Breaker
Figure 19 shows the LTC4252C-1 in a power limit circuit
breaking application. The SENSE pin is modulated by the
board
supply voltage, V
SUPPLY
. The D1 Zener voltage, V
Z
is set to be the same as the low supply operating volt-
age, V
SUPPLY(MIN)
= 43V. If the goal is to have the high
supply operating voltage, V
SUPPLY(MAX)
= 71V giving the
same power at V
SUPPLY(MIN)
, then resistors R4 and R6 are
selected using the ratio:
R6
R4
=
V
CB
V
SUPPLY(MAX)
(16)
If R6 is 27Ω, R4 is 38.3k. The peak circuit breaker power
limit is:
POWER
MAX
=
V
SUPPLY(MIN)
+V
SUPPLY(MAX)
( )
2
4• V
SUPPLY(MIN)
• V
SUPPLY(MAX)
•POWER
SUPPLY(MIN)
=1.064•POWER
SUPPLY(MIN)
(17)
when
V
SUPPLY
= 0.5 • (V
SUPPLY(MIN)
+ V
SUPPLY(MAX)
) = 57V.
The peak power at the fault current limit occurs at the supply
overvoltage threshold. The fault current limited power is:
POWER
FAULT
=
V
SUPPLY
R
S
• V
ACL
– V
SUPPLY
–V
Z
( )
•
R6
R4
(18)
TIMER
GATE
SENSE
SS
DRAIN
V
TMRH
V
DRNCL
V
ACL
V
CB
V
DRNL
V
GS(th)
V
IN
– V
GATEH
V
TMRL
4252B12 F18
PWRGD
5.8µA
58µA
58µA
TIMER
GATE
SENSE
SS
DRAIN
V
TMRH
V
DRNCL
V
CB
V
ACL
V
DRNL
V
GS(th)
V
IN
– V
GATEH
V
TMRL
PWRGD
5.8µA
58µA
58µA
12 34 567 7a 8 9 10 11
END OF INTIAL TIMING CYCLE
12 3 4 5 6 7 8 9 10 11
END OF INTIAL TIMING CYCLE
20 • V
OS
20 • (V
CB
+ V
OS
)
20 • (V
ACL
+ V
OS
)
20 • V
OS
20 • (V
CB
+ V
OS
)
20 • (V
ACL
+ V
OS
)
230µA + 8 • I
DRN
230µA + 8 • I
DRN
Figure 18. Soft-Start Timing (All Waveforms Are Referenced to V
EE
)
(18a) Without External C
SS
(18b) With External C
SS
LTC4252B-1/LTC4252B-2
LTC4252C-1/LTC4252C-2
30
4252b12f
APPLICATIONS INFORMATION
4252B12 F19
–48RTN
UV
OV
V
EE
V
IN
SENSESS
TIMER GATE
PWRGD
DRAIN
LTC4252C-1
R1
392k
1%
R2
30.1k
1%
C
T
0.68µF
C
SS
68nF
C
C
10nF
–48V
R
S
0.02Ω
Q1
IRF530S
V
OUT
R
C
10Ω
R5
100k
R4
38.3k
D1
BZV85C43
R
IN
3× 1.8k
1/4W EACH
1
9
8
10
3
2
7
6
4
5
C1
10nF
C
IN
1µF
C
L
100µF
–48RTN
(SHORT PIN)
+
R
D
1M
R6 27Ω
LOAD
EN
*
*FMMT493
**DIODES, INC
†
RECOMMENDED FOR HARSH ENVIRONMENTS
D
IN
†
DDZ13B
**
Figure 19. Power Limit Circuit Breaking Application
Circuit Breaker with Foldback Current Limit
Figure 20 shows the LTC4252C in a foldback current
limit application. When V
OUT
is shorted to the –48V RTN
supply, current flows through resistors R4 and R5. This
results in a voltage drop across R5 and a corresponding
reduction in voltage drop across the sense resistor, R
S
,
as the ACL amplifier servos the sense voltage between
the SENSE and V
EE
pins to about 60mV. The short-circuit
current through R
S
reduces as the V
OUT
voltage increases
during an output short-circuit condition. Without foldback
current limiting resistor R5, the current is limited to 3A
during analog current limit. With R5, the short-circuit
current is limited to 0.5A when V
OUT
is shorted to 71V.
Inrush Control Without a Sense
Resistor
During Power-Up
Figure 21 shows the LTC4252C in an application where the
inrush current is controlled without a sense resistor during
power-up. This setup is suitable only for applications that
don’t require short-circuit protection from the LTC4252C.
Resistor R4 and capacitor C2 act as a feedback network
to accurately control the inrush current. The C2 capacitor
can be calculated with the
following equation:
C2=
I
GATE
•C
L
I
INRUSH
(19)
where I
GATE
= 58µA and C
L
is the total load capacitance.
Capacitor C3 and resistor R4 prevent Q1 from momen-
tarily turning on when the power pins first make contact.
Without C3 and R4, capacitor C2 pulls the gate of Q1 up
to a voltage roughly equal to V
EE
• C2/C
GS(Q1)
before the
LTC4252C powers up. By placing capacitor C3 in parallel
with the gate capacitance of Q1 and isolating them from
C2 using resistor R4, the problem is solved. The value of
C3 is given by:
C3=
V
SUPPLY(MAX)
V
GS(TH),Q1
• C2+C
GD(Q1)
( )
(20)
C3 ≈ 35 • C2 for V
SUPPLY(MAX)
= 71V
where V
GS(TH),Q1
is the MOSFET’s minimum gate threshold
and V
SUPPLY(MAX)
is the maximum operating input voltage.
Diode-ORing
Figure 22 shows the LTC4252B used as diode-oring with
Hot Swap capability in a dual –48V power supply applica-
tion. The conventional diode-OR method uses two high
power diodes and heat sinks to contain
the large heat
dissipation of the diodes. With the LTC4252B controlling
the external FETs Q2 and Q3 in a diode-OR manner, the
small turn-on voltage across the fully enhanced Q2 and
Q3 reduces the power dissipation significantly.
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LTC4252CIMS-2#TRPBF

Mfr. #:
Buy LTC4252CIMS-2#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Neg V Hot Swap Cntrs
Lifecycle:
New from this manufacturer.
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