Si53156
16 Rev. 1.2
12 DIFF1 O, DIF 0.7 V, 100 MHz differential clock.
13 VDD PWR 3.3 V power supply.
14 DIFF2 O, DIF 0.7 V, 100 MHz differential clock.
15 DIFF2
O, DIF 0.7 V, 100 MHz differential clock.
16 VDD PWR 3.3 V power supply.
17 DIFF3
O, DIF 0.7 V, 100 MHz differential clock.
18 DIFF3 O, DIF 0.7 V, 100 MHz differential clock.
19 DIFF4
O, DIF 0.7 V, 100 MHz differential clock.
20 DIFF4 O, DIF 0.7 V, 100 MHz differential clock.
21 VDD PWR 3.3 V power supply.
22 DIFF5
O, DIF 0.7 V, 100 MHz differential clock.
23 DIFF5 O, DIF 0.7 V, 100 MHz differential clock.
24 VDD PWR 3.3 V power supply.
25 SCLK I SMBus compatible SCLOCK.
26 SDATA I/O SMBus compatible SDATA.
27 CKPWRGD_PDB I, PU
3.3 V LVTTL input. This pin is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. A real-time
active low input for asserting power down (PDB) and disabling all outputs
(internal 100 k pull-up).
28 VDD PWR 3.3 V power supply.
29 DIFFIN I
0.7 V Differential True Input, typically 100 MHz. Input frequency range
100 to 210 MHz.
30 DIFFIN
O
0.7 V Differential Complement Input, typically 100 MHz. Input frequency
range 100 to 210 MHz.
31 OE0 I,PU
Active high input pin enables DIFF0 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
32 OE1 I,PU
Active high input pin enables DIFF1 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
33 GND GND Ground for bottom pad of the IC.
Table 6. Si53156 32-Pin QFN Descriptions
Pin # Name Type Description
