MC14517BDWR2

© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 9
1 Publication Order Number:
MC14517B/D
MC14517B
Dual 64-Bit Static Shift
Register
The MC14517B dual 64−bit static shift register consists of two
identical, independent, 64−bit registers. Each register has separate clock
and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data
at the data input is entered by clocking, regardless of the state of the write
enable input. An output is disabled (open circuited) when the write enable
input is high. During this time, data appearing at the data input as well as
the 16−bit, 32−bit, and 48−bit taps may be entered into the device by
application of a clock pulse. This feature permits the register to be loaded
with 64 bits in 16 clock periods, and also permits bus logic to be used.
This device is useful in time delay circuits, temporary memory storage
circuits, and other serial shift register applications.
Features
Diode Protection on All Inputs
Fully Static Operation
Output Transitions Occur on the Rising Edge of the Clock Pulse
Exceedingly Slow Input Transition Rates May Be Applied to the
Clock Input
3−State Output at 64th−Bit Allows Use in Bus Logic Applications
Shift Registers of any Length may be Fully Loaded with 16 Clock
Pulses
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Parameter Symbol Value Unit
DC Supply Voltage Range V
DD
0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V
in
, V
out
−0.5 to V
DD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
I
in
, I
out
±10 mA
Power Dissipation per Package (Note 1) P
D
500 mW
Operating Temperature Range T
A
55 to +125 °C
Storage Temperature Range T
stg
65 to +150 °C
Lead Temperature (8−Second Soldering) T
L
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: Plastic “D/DW” Package: –7.0 mW/_C From 65_C to
125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
) V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
Device Package Shipping
ORDERING INFORMATION
http://onsemi.com
MC14517BDWR2G SOIC−16 WB
(Pb−Free)
1000 /
Tape & Reel
MC14517BDWG SOIC−16 WB
(Pb−Free)
47 Units/Rail
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
s
Brochure, BRD8011/D.
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
MARKING DIAGRAM
SOIC−16 WB
DW SUFFIX
CASE 751G
16
1
14517B
AWLYYWWG
1
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
C
B
WE
B
Q48
B
Q16
B
V
DD
D
B
Q32
B
Q64
B
C
A
WE
A
Q48
A
Q16
A
V
SS
Q32
A
Q64
A
D
A
NLV14517BDWR2G SOIC−16 WB
(Pb−Free)
1000 /
Tape & Reel
MC14517B
http://onsemi.com
2
FUNCTIONAL TRUTH TABLE (X = Don’t Care)
Clock
Write
Enable
Data 16−Bit Tap 32−Bit Tap 48−Bit Tap 64−Bit Tap
0 0 X Content of 16−Bit
Displayed
Content of 32−Bit
Displayed
Content of 48−Bit
Displayed
Content of 64−Bit
Displayed
0 1 X High Impedance High Impedance High Impedance High Impedance
1 0 X Content of 16−Bit
Displayed
Content of 32−Bit
Displayed
Content of 48−Bit
Displayed
Content of 64−Bit
Displayed
1 1 X High Impedance High Impedance High Impedance High Impedance
0 Data entered
into 1st Bit
Content of 16−Bit
Displayed
Content of 32−Bit
Displayed
Content of 48−Bit
Displayed
Content of 64−Bit
Displayed
1 Data entered
into 1st Bit
Data at tap
entered into 17−Bit
Data at tap
entered into 33−Bit
Data at tap
entered into 49−Bit
High Impedance
0 X Content of 16−Bit
Displayed
Content of 32−Bit
Displayed
Content of 48−Bit
Displayed
Content of 64−Bit
Displayed
1 X High Impedance High Impedance High Impedance High Impedance
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
Characteristic
Symbo
l
V
DD
Vdc
− 55_C 25_C 125_C
Unit
Min Max Min
Typ
(Note 2)
Max Min Max
Output Voltage “0” Level
V
in
= V
DD
or 0
“1” Level
V
in
= 0 or V
DD
V
OL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
V
OH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage “0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
V
IL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
Vdc
V
IH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc) Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc) Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OH
5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
–2.4
–0.51
–1.3
–3.4
–4.2
–0.88
–2.25
–8.8
–1.7
–0.36
–0.9
–2.4
mAdc
I
OL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current I
in
15 ±0.1 ±0.00001 ±0.1 ±1.0
mAdc
Input Capacitance (V
in
= 0) C
in
5.0 7.5 pF
Quiescent Current (Per Package) I
DD
5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
mAdc
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
I
T
= (4.2 mA/kHz) f + I
DD
I
T
= (8.8 mA/kHz) f + I
DD
I
T
= (13.7 mA/kHz) f + I
DD
mAdc
Three−State Leakage Current I
TL
15 ±0.1 ±0.0001 ±0.1 ±3.0
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF: I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk where: I
T
is in mA (per package), C
L
in pF,
V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.004.
MC14517B
http://onsemi.com
3
SWITCHING CHARACTERISTICS (Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Symbol V
DD
Min
Typ
(Note 6)
Max Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.65 ns/pF) C
L
+ 9.5 ns
t
TLH
, t
THL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 390 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 177 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 115 ns
t
PLH
, t
PHL
5.0
10
15
475
210
140
770
300
215
ns
Clock Pulse Width t
WH
5.0
10
15
330
125
100
170
75
60
ns
Clock Pulse Frequency f
cl
5.0
10
15
3.0
6.7
8.3
1.5
4.0
5.3
MHz
Clock Pulse Rise and Fall Time t
TLH
, t
THL
5.0
10
15
See (Note 7)
Data to Clock Setup Time t
su
5.0
10
15
0
10
15
– 40
– 15
0
ns
Data to Clock Hold Time t
h
5.0
10
15
150
75
35
75
25
10
ns
Write Enable to Clock Setup Time t
su
5.0
10
15
400
200
110
170
65
50
ns
Write Enable to Clock Release Time t
rel
5.0
10
15
380
180
100
160
55
40
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
7. When shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than the rise and fall
time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage.
Figure 1. Power Dissipation Test Circuit and Waveform
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
V
DD
Q16 Q32 Q48 Q64
Q16 Q32 Q48 Q64
V
DD
V
DD
V
SS
V
SS
D
C
WE
D
C
WE
V
SS
I
D
D
C
50 mF
REPETITIVE WAVEFORM
C
D
f
o
(f = 1/2 f
o
)

MC14517BDWR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC SHIFT REG DUAL 64BIT 16-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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