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74AHC86PW,112
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
74AHC_AHCT86_2
© NXP B.V
. 2007. All rights reserved.
Product data sheet
Rev
. 02 — 15 No
vember 2007
9 of 14
NXP Semiconductors
74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
12.
P
acka
g
e outline
Fig 8.
P
ackage outline SO
T108-1 (SO14)
UNIT
A
max.
A
1
A
2
A
3
b
p
cD
(1)
E
(1)
(1)
eH
E
LL
p
QZ
y
w
v
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25
0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
w
M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
7
8
1
14
y
076E06
MS-012
pin 1 index
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.35
0.34
0.16
0.15
0.05
1.05
0.041
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.25
0.01
0.004
0.039
0.016
99-12-27
03-02-19
0
2.5
5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
74AHC_AHCT86_2
© NXP B.V
. 2007. All rights reserved.
Product data sheet
Rev
. 02 — 15 No
vember 2007
10 of 14
NXP Semiconductors
74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
Fig 9.
P
ackage outline SO
T402-1 (TSSOP14)
UNIT
A
1
A
2
A
3
b
p
cD
(1)
E
(2)
(1)
eH
E
LL
p
QZ
y
w
v
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.72
0.38
8
0
o
o
0.13
0.1
0.2
1
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1
MO-153
99-12-27
03-02-18
w
M
b
p
D
Z
e
0.25
17
14
8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v
M
A
X
A
y
0
2.5
5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
A
max.
1.1
pin 1 index
74AHC_AHCT86_2
© NXP B.V
. 2007. All rights reserved.
Product data sheet
Rev
. 02 — 15 No
vember 2007
11 of 14
NXP Semiconductors
74AHC86; 74AHCT86
Quad 2-input EXCLUSIVE-OR gate
Fig 10.
P
ackage outline SO
T762-1 (DHVQFN14)
terminal 1
index area
0.5
1
A
1
E
h
b
UNIT
y
e
0.2
c
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
mm
3.1
2.9
D
h
1.65
1.35
y
1
2.6
2.4
1.15
0.85
e
1
2
0.30
0.18
0.05
0.00
0.05
0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1
MO-241
- - -
- - -
0.5
0.3
L
0.1
v
0.05
w
0
2.5
5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A
(1)
max.
A
A
1
c
detail X
y
y
1
C
e
L
E
h
D
h
e
e
1
b
26
13
9
8
7
1
14
X
D
E
C
B
A
02-10-17
03-01-27
terminal 1
index area
A
C
C
B
v
M
w
M
E
(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D
(1)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
74AHC86PW,112
Mfr. #:
Buy 74AHC86PW,112
Manufacturer:
Nexperia
Description:
Logic Gates QUAD 2 INPUT EXCL OR
Lifecycle:
New from this manufacturer.
Delivery:
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EMS
Payment:
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