Data Sheet ADuM3200/ADuM3201
Rev. F | Page 17 of 24
APPLICATION INFORMATION
PC BOARD LAYOUT
The ADuM3200/ADuM3201 digital isolators require no
external interface circuitry for the logic interfaces. Power
supply bypassing is strongly recommended at the input and
output supply pins. The capacitor value must be between
0.01 μF and 0.1 μF. The total lead length between both ends
of the capacitor and the input power supply pin must not
exceed 20 mm. See the AN-1109 Application Note for board
layout guidelines.
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
System-level ESD reliability (for example, per IEC 61000-4-x)
is highly dependent on system design which varies widely by
application. The ADuM3200/ADuM3201 incorporate many
enhancements to make ESD reliability less dependent on system
design. The enhancements include:
ESD protection cells added to all input/output interfaces.
Key metal trace resistances reduced using wider geometry
and paralleling of lines with vias.
The SCR effect inherent in CMOS devices minimized by
use of guarding and isolation technique between PMOS
and NMOS devices.
Areas of high electric field concentration eliminated using
45° corners on metal traces.
Supply pin overvoltage prevented with larger ESD clamps
between each supply pin and the respective ground.
While the ADuM3200/ADuM3201 improve system-level
ESD reliability, they are no substitute for a robust system-level
design. See the AN-793 Application Notes, ESD/Latch-Up
Considerations with iCoupler Isolation Product, for detailed
recommendations on board layout and system-level design.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation
delay to a logic high.
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
05927-012
Figure 12. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of
how accurately the input signal timing is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM3200/ADuM3201 component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM3200/
ADuM3201 components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is therefore either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions of more than ~1 μs at the input, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses for more than about 5 μs, the input
side is assumed to be unpowered or nonfunctional, in which
case, the isolator output is forced to a default state (see Table 32
and Table 33) by the watchdog timer circuit.
The ADuM3200/ADuM3201 are extremely immune to external
magnetic fields. The limitation on the ADuM3200/ADuM3201
magnetic field immunity is set by the condition in which induced
voltage in the transformer receiving coil is sufficiently large to
either falsely set or reset the decoder. The following analysis defines
the conditions under which this can occur. The 3 V operating
condition of the ADuM3200/ADuM3201 is examined because
it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ/dt) ∑π r
n
2
, n = 1, 2,…, N
where:
β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil.
r
n
is the radius of the nth turn in the receiving coil (cm).
