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ADM695ARZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
ADM690–ADM695
REV. A
–10–
+APPLICATION INFORMATION
Increasing the Drive Current
If the continuous output current requirements at V
OUT
exceed
100 mA or if a lower V
CC
–V
OUT
voltage differential is desired,
an external PNP pass transistor may be connected in parallel
with the internal transistor. The BATT ON output (ADM691/
ADM693/ADM695) can directly drive the base of the external
transistor.
V
OUT
V
CC
BATTERY
+5V
INPUT
POWER
0.1µF0.1µF
BATT
ON
V
BATT
PNP TRANSISTOR
ADM691
ADM693
ADM695
Figure 17. Increasing the Drive Current
Using a Rechargeable Battery for Back Up
If a capacitor or a rechargeable battery is used for back up then
the charging resistor should be connected to V
OUT
since this
eliminates the discharge path that would exist during power
down if the resistor is connected to V
CC
.
V
OUT
V
CC
RECHARGEABLE
BATTERY
+5V
INPUT
POWER
0.1µF
0.1µF
V
BATT
ADM69x
R
I =
V
OUT
– V
BATT
R
Figure 18. Rechargeable Battery
Adding Hysteresis to the Power Fail Comparator
For increased noise immunity, hysteresis may be added to the
power fail comparator. Since the comparator circuit is nonin-
verting, hysteresis can be added simply by connecting a resistor be-
tween the
PFO output and the PFI input as shown in Figure 19.
When
PFO is low, resistor R
3
sinks current from the summing
junction at the PFI pin. When
PFO is high, the series combina-
tion of R
3
and R
4
source current into the PFI summing junc-
tion. This results in differing trip levels for the comparator.
ADM69x
R
2
1.3V
PFO
R
1
7805
R
4
R
3
+7V TO +15V
INPUT
POWER
+5V
PFI
V
CC
TO
µP NMI
5V
0V
0V
V
L
V
H
V
IN
PFO
V
H
= 1.3V
(
1+ ––– + –––
)
V
L
= 1.3V
(
1+ ––– – –––––––––––––
)
ASSUMING R
4
< <
R
3
THEN
HYSTERESIS V
H
– V
L
= 5V
(
–––
)
R
1
R
2
R
1
R
3
R
1
R
2
R
1
R
2
R
1
(5V – 1.3V)
1.3V (R
3 +
R
4
)
Figure 19. Adding Hysteresis to the Power Fail Comparator
Monitoring the Status of the Battery
The power fail comparator can be used to monitor the status of
the backup battery instead of the power supply if desired. This
is shown in Figure 20. The PFI input samples the battery volt-
age and generates an active low
PFO signal when the battery
voltage drops below a chosen threshold. It may be necessary to
apply a test load in order to determine the loaded battery volt-
age. This can be done under processor control using
CE
OUT.
Since CE
OUT
is forced high during the battery backup mode, the
test load will not be applied to the battery while it is in use, even
if the microprocessor is not powered.
ADM690–ADM695
REV. A
–11–
ADM69x
CE
IN
PFO
PFI
V
CC
FROM µP I/O PIN
APPLIES TEST LOAD
TO BATTERY
LOW BATTERY
SIGNAL TO
µP I/O PIN
+5V INPUT
POWER
V
BATT
CE
OUT
BATTERY
20kΩ
OPTIONAL
TEST LOAD
10MΩ
10MΩ
Figure 20. Monitoring the Battery Status
Alternate Watchdog Input Drive Circuits
The watchdog feature can be enabled and disabled under pro-
gram control by driving WDI with a 3-state buffer (Figure 21a).
When three-stated, the WDI input will float thereby disabling
the watchdog timer.
WDI
ADM69x
WATCHDOG
STROBE
CONTROL
INPUT
Figure 21a. Programming the Watchdog Input
This circuit is not entirely foolproof, and it is possible that a
software fault could erroneously 3-state the buffer. This would
then prevent the ADM69x from detecting that the microproces-
sor is no longer operating correctly. In most cases a better
method is to extend the watchdog period rather than disabling
the watchdog. This may be done under program control using
the circuit shown in Figure 21b. When the control input is high,
the OSC SEL pin is low and the watchdog timeout is set by the
external capacitor. A 0.01 µF capacitor sets a watchdog timeout
delay of 100 seconds. When the control input is low, the OSC
SEL pin is driven high, selecting the internal oscillator. The
100 ms or the 1.6 s period is chosen, depending on which diode
in Figure 21b is used. With D1 inserted the internal timeout is
set at 100 ms, while with D2 inserted the timeout is set at 1.6 s.
OSC IN
OSC SEL
ADM69x
CONTROL
INPUT*
D1
D2
*LOW = INTERNAL TIMEOUT
HIGH = EXTERNAL TIMEOUT
Figure 21b. Programming the Watchdog Input
Replacing the Backup Battery
When changing the backup battery with system power on, spuri-
ous resets can occur when the battery is removed. This occurs
because the leakage current flowing out of the V
BATT
pin will
charge up the stray capacitance. If the voltage on V
BATT
reaches
within 50 mV of V
CC
, a reset pulse is generated.
If spurious resets during battery replacement are acceptable,
then no action is required. If not, then one of the following
solutions should be considered:
1. A capacitor from V
BATT
to GND. This gives time while the
capacitor is charging up to replace the battery. The leakage
current will charge up the external capacitor towards the V
CC
level. The time taken is related to the charging current, the
size of external capacitor and the voltage differential between
the capacitor and the charging voltage supply.
t = C
EXT
× V
DIFF
/I
The maximum leakage (charging) current is 1 µA over tem-
perature and V
DIFF
= V
CC
–V
BATT
. Therefore, the capacitor
size should be chosen such that sufficient time is available to
make the battery replacement.
C
EXT
= T
REQD
(1 µA/(V
CC
–V
BATT
))
If a replacement time of 5 seconds is allowed and assuming a
V
CC
of 4.5 V and a V
BATT
of 3 V
C
EXT
= 3.33 µF
ADM69x
V
BATT
BATTERY
C
EXT
Figure 22a. Preventing Spurious RESETS During
Battery Replacement
2. A resistor from V
BATT
to GND. This will prevent the voltage
on V
BATT
from rising to within 50 mV of V
CC
during battery
replacement.
ADM690–ADM695
REV. A
–12–
ADM690
ADM692
ADM694
R
2
R
1
PFO
+5V
V
CC
CMOS RAM
POWER
I/O LINE
µP NMI
µP RESET
µP SYSTEM
µP POWER
V
OUT
RESET
WDI
GND
PFI
V
BATT
BATTERY
+
0.1µF
Figure 23a. ADM690/ADM692/ADM694 Typical Application
Circuit A
Figure 23b shows a similar application but in this case the PFI
input monitors the unregulated input to the 7805 voltage regu-
lator. This gives an earlier warning of an impending power fail-
ure. It is useful with processors operating at low speeds or
where there are a significant number of housekeeping tasks to be
completed before the power is lost.
ADM690
ADM692
ADM694
R
2
R
1
PFO
7805
INPUT
POWER
V > 8V
+5V
V
CC
CMOS RAM
POWER
I/O LINE
µP NMI
µP RESET
µP SYSTEM
µP POWER
V
OUT
RESET
WDI
GND
PFI
V
BATT
0.1µF
BATTERY
0.1µF
Figure 23b. ADM690/ADM692/ADM694 Typical Application
Circuit B
ADM691, ADM693, ADM695
A typical connection for the ADM691/ADM693/ADM695 is
shown in Figure 24. CMOS RAM is powered from V
OUT
. When
5 V power is present this is routed to V
OUT
. If V
CC
fails then
V
BATT
is routed to V
OUT
. V
OUT
can supply up to 100 mA from
V
CC
, but if more current is required, an external PNP transistor
can be added. When V
CC
is higher than V
BATT
, the BATT ON
output goes low, providing up to 25 mA of base drive for the
external transistor. A 0.1 µF capacitor is connected to V
OUT
to
supply the transient currents for CMOS RAM. When V
CC
is
lower than V
BATT
, an internal 20 Ω MOSFET connects the
backup battery to V
OUT
.
R =(V
CC
– 50 mV)/1 µA
Note that the resistor will discharge the battery slightly. With a
V
CC
supply of 4.5 V, a suitable resistor is 4.3 MΩ. With a 3 V
battery this will draw around 700 nA. This will be negligible in
most cases.
ADM69x
V
BATT
BATTERY
R
Figure 22b. Preventing Spurious RESETS During Battery
Replacement
TYPICAL APPLICATIONS
ADM690, ADM692 AND ADM694
Figure 23 shows the ADM690/ADM692/ADM694 in a typical
power monitoring, battery backup application. V
OUT
powers the
CMOS RAM. Under normal operating conditions with V
CC
present, V
OUT
is internally connected to V
CC
. If a power failure
occurs, V
CC
will decay and V
OUT
will be switched to V
BATT
thereby maintaining power for the CMOS RAM. A RESET
pulse is also generated when V
CC
falls below 4.65 V for the
ADM690/ADM694 or 4.4 V for the ADM692.
RESET will
remain low for 50 ms (200 ms for ADM694) after V
CC
returns
to 5 V.
The watchdog timer input (WDI) monitors an I/O line from the
µP system. This line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line indi-
cates that the µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
If the watchdog timer is not needed, the WDI input should be
left floating.
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is com-
pared with a precision 1.3 V internal reference. If the input volt-
age drops below 1.3 V, a power fail output (
PFO) signal is
generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage V
T
.
V
T
= (1.3 R
1
/R
2
) + 1.3 V
R
1
/R
2
= (V
T
/1.3) – 1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ADM695ARZ

Mfr. #:
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Manufacturer:
Analog Devices / Linear Technology
Description:
Supervisory Circuits 5V CMOS MPU IC Battery Mgmt
Lifecycle:
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