List of figures STM1810/1811/1812/1813/1815/1816/1817/1818
4/25 Doc ID11464 Rev 8
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. SOT23-3 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Push-pull active-low output (STM1810/1812/1815/1817). . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Open-drain, active-low output (STM1811/1816) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Open-drain, active-low output (bidirectional, manual reset detect, STM1813/1818) . . . . . . 7
Figure 7. Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Push-button manual reset with MR
detect (STM1813/1818) . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Manual reset timing diagram, switch bounce/debounce (STM1813/1818). . . . . . . . . . . . . 11
Figure 10. Interfacing MCUs with bidirectional reset pins (RST
, open-drain, STM1811/1816) . . . . . . 11
Figure 11. Valid reset (RST
) output down to V
CC
= 0 V (push-pull). . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 12. Valid reset (RST) output down to V
CC
= 0 V (push-pull). . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13. Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 14. Normalized reset time-out period (t
rec
) vs. temperature - V
OD
= V
TH
– V
CC
. . . . . . . . . . . 13
Figure 15. V
CC
-to-reset output delay vs. temperature - V
OD
= V
TH
– V
CC
. . . . . . . . . . . . . . . . . . . . . 14
Figure 16. Voltage output low vs. I
SINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 17. Voltage output high vs. I
SOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18. Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19. Max. transient duration NOT causing reset pulse vs. reset threshold overdrive. . . . . . . . . 16
Figure 20. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. SOT23-3 – 3-lead small outline transistor package outline . . . . . . . . . . . . . . . . . . . . . . . . 20