IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
ICS932S208
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
3
Pin Description (continued)
PIN # PIN NAME PIN TYPE DESCRIPTION
29 3V66_4/VCH OUT
66.66MHz clock output for AGP support. AGP-PCI should be aligned
with a skew window tolerance of 500ps.
VCH is 48MHz clock out
ut for video controller hub.
30 SDATA I/O Data
in for I2C circuitr
5V tolerant
31 48MHz_USB OUT 48MHz clock out
ut.
32 48MHz_DOT OUT 48MHz clock out
ut.
33 GND PWR Ground
in.
34 VDD48 PWR Power
in for the 48MHz out
ut.3.3V
35 Vtt_PWRGD# IN
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low in
ut.
36 VDD PWR Power su
l
for SRC clocks, nominal 3.3V
37 SRCCLKC OUT
Complement clock of differential pair for S-ATA support.
+/- 300
m accurac
re
uired.
38 SRCCLKT OUT
True clock of differential pair for S-ATA support.
+/- 300
m accurac
re
uired.
39 GND PWR Ground
in.
40
CPUCLKC0 OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
41 CPUCLKT0 OUT
True clock of differential pair CPU outputs. These are current mode
out
uts. External resistors are re
uired for volta
e bias.
42 VDDCPU PWR Su
l
for CPU clocks, 3.3V nominal
43 CPUCLKC1 OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
44 CPUCLKT1 OUT
True clock of differential pair CPU outputs. These are current mode
out
uts. External resistors are re
uired for volta
e bias.
45 GND PWR Ground
in.
46 CPUCLKC2 OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
47 CPUCLKT2 OUT
True clock of differential pair CPU outputs. These are current mode
out
uts. External resistors are re
uired for volta
e bias.
48 VDDCPU PWR Su
l
for CPU clocks, 3.3V nominal
49 CPUCLKC3 OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
50 CPUCLKT3 OUT
True clock of differential pair CPU outputs. These are current mode
out
uts. External resistors are re
uired for volta
e bias.
51 FS_A IN Fre
uenc
select
in, see Fre
uenc
table for functionalit
52 IREF OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
53 GND PWR Ground
in.
54 GNDA PWR Ground
in for core.
55 VDDA PWR 3.3V
ower for the PLL core.
56 FS_B IN Frequency select pin, see Frequency table for functionality