TC913A/TC913B
DS21482D-page 4 2001-2012 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Pin No.
(8-Pin PDIP)
(8-Pin SOIC)
Symbol Description
1OUT AOutput
2 -IN A Inverting Input
3 +IN A Non-inverting Input
4V
SS
Negative Power Supply
5 +IN B Non-inverting Input
6 -IN B Inverting Input
7OUT BOutput
8V
DD
Positive Power Supply
2001-2012 Microchip Technology Inc. DS21482D-page 5
TC913A/TC913B
3.0 DETAILED DESCRIPTION
3.1 Theory of Operation
Each of the TC913’s two Op Amps actually consists of
two amplifiers. A main amplifier is always connected
from the input to the output. A separate nulling amplifier
alternately nulls its own offset and then the offset of the
amplifier. Since each amplifier is continuously being
nulled, offset voltage drift with time, temperature and
power supply variations is greatly reduced.
All nulling circuitry is internal and the nulling operation
is transparent to the user. Offset nulling voltages are
stored on two internal capacitors. An internal oscillator
and control logic, shared by the TC913’s two amplifiers,
control the nulling process.
3.2 Pin Compatibility
The TC913 pinout is compatible with OP-14, LM358,
MC1458, LT1013, TLC322, and similar dual Op Amps.
In many circuits operating from single or ±5V supplies,
the TC913 is a drop-in replacement offering DC
performance rivaling that of the best single Op Amps.
The TC913’s amplifiers include a low-impedance class
AB output buffer. Some previous CMOS chopper
amplifiers used a high-impedance output stage which
made open-loop gain dependent on load resistance.
The TC913’s open-loop gain is not dependent on load
resistance.
3.3 Overload Recovery
The TC913 recovers quickly from output saturation.
Typical recovery time from positive output saturation is
20 msec. Negative output saturation recovery time is
typically 5 msec.
3.4 Avoiding Latch-up
Junction-isolated CMOS circuits inherently contain a
parasitic p-n-p-n transistor circuit. Voltages exceeding
the supplies by 0.3V should not be applied to the
device pins. Larger voltages can turn the p-n-p-n
device on, causing excessive device power supply
current and power dissipation. The TC913’s power
supplies should be established at the same time or
before input signals are applied. If this is not possible,
input current should be limited to 0.1 mA to avoid
triggering the p-n-p-n structure.
TC913A/TC913B
DS21482D-page 6 2001-2012 Microchip Technology Inc.
4.0 TYPICAL CHARACTERISTICS
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
HORIZONTAL SCALE = 20 msec/DIV
Positive Overload Recovery Time
0V
OUTPUT =
2 V/DIV
INPUT INPUT
GAIN = –20
35
INPUT OFFSET VOLTAGE (µV)
-6
INPUT COMMON MODE VOLTAGE (V)
Input Offset Voltage vs.
Common Mode Voltage
30
25
20
15
10
5
0
-5 -4 -3 -2 -1 0 1 2 3 4
V
A
= ±5V
T
A
= +25°C
SUPPLY CURRENT (µA)
± SUPPLY VOLTAGE (V)
Supply Current vs. ± Supply Voltage
HORIZONTAL SCALE = 20 msec/DIV
Negative Overload Recovery Time
R
L
= 10 k
T
A
= +25°C
W
INPUT
0V
OUTPUT
= 2 V/DIV
50
CLOSED-LOOP GAIN (dB)
10k
FREQUENCY (Hz)
Gain and Phase vs. Frequency
40
30
20
10
0
-10
-20
-30
-40
100k 1M 10M
PHASE
GAIN
V
S
= ±5V
T
A
= +25°C
R
L
= 10 k
W
225
PHASE (deg)
180
135
90
45
0
-45
-90
-135
-180
± OUTPUT VOLTAGE (V)
100
LOAD RESISTANCE (W)
Output Voltage Swing vs.
Load Resistance
5.0
V
S
= ±5V
T
A
= +25°C
-SWING
+SWING
4.2
3.4
2.6
1.8
1.0
1k 10k 100k
1M
1200
1000
800
600
400
200
0
23 54678
T
A
= +25°C
Gain = –20

TC913BCOA713

Mfr. #:
Manufacturer:
Microchip Technology
Description:
Operational Amplifiers - Op Amps Dual Low VOS w/Caps
Lifecycle:
New from this manufacturer.
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