C8051F330-GDI

C8051F330-GDI
4 Rev. 1.2
P0.6/
CNVSTR
21 D I/O or
A In
D In
Port 0.6.
ADC0 External Convert Start or IDA0 Update Source Input.
P0.7 20 D I/O or
A In
Port 0.7.
P1.0 18 D I/O or
A In
Port 1.0.
P1.1 16 D I/O or
A In
Port 1.1.
P1.2 15 D I/O or
A In
Port 1.2.
P1.3 14 D I/O or
A In
Port 1.3.
P1.4 11 D I/O or
A In
Port 1.4.
P1.5 10 D I/O or
A In
Port 1.5.
P1.6 9 D I/O or
A In
Port 1.6.
P1.7 8 D I/O or
A In
Port 1.7.
Table 2.1. Pin Definitions for the C8051F330-GDI (Continued)*
Name
Physical
Pad
Number
Type Description
*Note: For a complete description of the functionality of all pins, refer to the C8051F330/1/2/3/4/5 technical data
sheet.
Rev. 1.2 5
C8051F330-GDI
3. Bonding Instructions
Table 3.1. C8051F330-GDI Pad Connections
Physical Pad
Number
Package Pin
Number (20-QFN)
Package Pin
Name
Physical Pad X
(µm)
Physical Pad Y
(µm)
1 P0.0 1 –802.7 964.7
2 GND 2 –964.7 –61.2
3 GND 2 –964.7 –173.2
4 VDD 3 –964.7 –284.1
5 VDD 3 –964.7 –396.1
6 /RST/C2CK 4 –964.7 –587.7
7 P2.0/C2D 5 –964.7 –797.7
8 P1.7 6 –797.7 –964.7
9 P1.6 7 –627.7 –964.7
10 P1.5 8 –447.7 –964.7
11 P1.4 9 240.7 –964.7
12 Reserved* 396.7 –964.7
13 Reserved* 471.7 –964.7
14 P1.3 10 627.7 –964.7
15 P1.2 11 797.7 –964.7
16 P1.1 12 964.7 –797.7
17 Reserved* 964.7 70.05
18 P1.0 13 964.7 201.05
19 Reserved* 964.7 337.05
20 P0.7 14 964.7 627.7
21 P0.6 15 964.7 797.7
22 P0.5 16 797.7 964.7
23 P0.4 17 627.7 964.7
24 P0.3 18 447.7 964.7
25 P0.2 19 –79.9 964.7
26 P0.1 20 –622.7 964.7
*Note: Pins marked “Reserved” should not be connected.
C8051F330-GDI
6 Rev. 1.2
Figure 3.1. Example Die Bonding (QFN-20)

C8051F330-GDI

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Lifecycle:
New from this manufacturer.
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