LT1767/LT1767-1.8/
LT1767-2.5/LT1767-3.3/LT1767-5
14
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For more information www.linear.com/LT1767
applicaTions inForMaTion
Example: with V
IN
= 10V, V
OUT
= 5V and I
OUT
= 1A:
P
SW
=
0.27
( )
1
( )
2
5
( )
10
+ 17 • 10
−9
( )
1
( )
10
( )
1.25 • 10
6
( )
= 0.135+ 0.21= 0.34W
P
BOOST
=
5
( )
2
1/ 50
( )
10
= 0.05W
P
Q
=10 0.001
( )
= 0.01W
Total power dissipation is 0.34 + 0.05 + 0.01 = 0.4W.
Thermal resistance for LT1767 package is influenced
by the presence of internal or backside planes. With a
full plane under the package, thermal resistance for the
exposed pad
package will be about 40°C/W. No plane
will increase resistance to about 150°C/W. To calculate
die temperature, use the appropriate thermal resistance
number and add in worst-case ambient temperature:
T
J
= T
A
+ θ
JA
(P
TOT
)
When estimating ambient, remember the nearby catch
diode and inductor will also be dissipating power.
P
DIODE
=
V
F
V
IN
− V
OUT
I
LOAD
V
V
F
= Forward voltage of diode (assume 0.5V at 1A)
P
DIODE
=
0.5
12− 5
1
= 0.29W
Notice that the catch diode’s forward voltage contributes
a significant loss in the overall system efficiency. A larger,
lower V
F
diode can improve efficiency by several percent.
P
INDUCTOR
= (I
LOAD
) (L
DCR
)
L
DCR
= Inductor DC resistance (assume 0.1Ω)
P
INDUCTOR
= (1) (0.1) = 0.1W
Typical thermal resistance of the board is 35°C/W. At an
ambient temperature of 65°C,
T
j
= 65 + 40 (0.4) + 35 (0.39) = 95°C
If a true die temperature is required, a measurement of the
SYNC to GND pin resistance can be used. The SYNC pin
resistance across temperature must first be calibrated, with
no device power, in an oven. The same measurement can
then be used in operation to indicate the die temperature.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered – the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits, read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/
or catch diode, and connecting the V
C
compensation to a
ground track carrying significant switch current. In addition,
the theoretical analysis considers only first order non
-ideal
component
behavior. For these reasons, it is important
that a final stability check is made with production layout
and components.
The LT1767 uses current mode control to regulate the
output. This simplifies loop compensation. In particular,
the LT1767 does not require the ESR (equivalent series
resistance) of the output capacitor for stability, so you
are free to use ceramic capacitors to achieve low output
ripple and small circuit size. Frequency compensation is
provided by the components tied to the V
C
pin, as shown
in Figure 7. Generally a capacitor (C
C
) and a resistor (R
C
)
in series to ground are used. In addition, there may be
lower value capacitor (C
F
) in parallel.
Figure 7 also shows an equivalent circuit for the LT1767
control loop. The error amplifier is a transconductance
amplifier with finite output impedance. The power section,
consisting of the modulator, power switch and inductor,
is modeled as a transconductance amplifier generating an
output current proportional to the voltage at the V
C
pin.
Note that the output capacitor integrates this current, and
that the capacitor on the V
C
pin (C
C
) integrates the error
amplifier output current, resulting in two poles in the loop.
In most cases
a zero is required and comes from either
the
output capacitor ESR or from a resistor R
C
in series
