MAX5062/MAX5063/MAX5064
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
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where C
L
is the combined capacitive load at DH and
DL. V
DD
is the supply voltage and f
SW
is the switching
frequency of the converter. P
D
includes the power dis-
sipated in the internal bootstrap diode. The internal
power dissipation reduces by P
DIODE
, if an external
bootstrap Schottky diode is used. The power dissipa-
tion in the internal boost diode (when driving a capaci-
tive load) will be the charge through the diode per
switching period multiplied by the maximum diode for-
ward voltage drop (V
f
= 1V).
The total power dissipation when using the internal
boost diode will be P
D
and, when using an external
Schottky diode, will be P
D
- P
DIODE
. The total power
dissipated in the device must be kept below the maxi-
mum of 1.951W for the 12-pin TQFN package, 1.5W for
the 8-pin SO with exposed pad, and 0.471W for the
regular 8-pin SO package at T
A
= +70°C ambient.
Layout Information
The MAX5062/MAX5063/MAX5064 drivers source and
sink large currents to create very fast rise and fall
edges at the gates of the switching MOSFETs. The high
di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. Use
the following PC board layout guidelines when design-
ing with the MAX5062/MAX5063/MAX5064:
• It is important that the V
DD
voltage (with respect to
ground) or BST voltage (with respect to HS) does
not exceed 13.2V. Voltage spikes higher than 13.2V
from V
DD
to GND or BST to HS can damage the
device. Place one or more low ESL 0.1µF decou-
pling ceramic capacitors from V
DD
to GND
(MAX5062/MAX5063) or to PGND (MAX5064), and
from BST to HS as close as possible to the part. The
ceramic decoupling capacitors should be at least
20 times the gate capacitance being driven.
• There are two AC current loops formed between the
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from gate
to source when the gate is being pulled low. The
active current loop is from the MOSFET driver output
(DL or DH) to the MOSFET gate, to the MOSFET
source, and to the return terminal of the MOSFET dri-
ver (either GND or HS). When the gate of the MOS-
FET is being pulled high, the active current loop is
from the MOSFET driver output, (DL or DH), to the
MOSFET gate, to the MOSFET source, to the return
terminal of the drivers decoupling capacitor, to the
positive terminal of the decoupling capacitor, and to
the supply connection of the MOSFET driver. The
decoupling capacitor will be either the flying capaci-
tor connected between BST and HS or the decou-
pling capacitor for V
DD
. Care must be taken to
minimize the physical distance and the impedance of
these AC current paths.
• Solder the exposed pad of the TQFN (MAX5064) or
SO (MAX5062C/D and MAX5063C/D) package to a
large copper plane to achieve the rated power dissi-
pation. Connect AGND and PGND at one point near
V
DD
’s decoupling capacitor return.
