MAX5062/MAX5063/MAX5064
Undervoltage Lockout
Both the high- and low-side drivers feature undervolt-
age lockout (UVLO). The low-side driver’s UVLO
LOW
threshold is referenced to GND and pulls both driver
outputs low when V
DD
falls below 6.8V. The high-side
driver has its own undervoltage lockout threshold
(UVLO
HIGH
), referenced to HS, and pulls DH low when
BST falls below 6.4V with respect to HS.
During turn-on, once V
DD
rises above its UVLO thresh-
old, DL starts switching and follows the IN_L logic input.
At this time, the bootstrap capacitor is not charged and
the BST-to-HS voltage is below UVLO
BST
. For synchro-
nous buck and half-bridge converter topologies, the
bootstrap capacitor can charge up in one cycle and
normal operation begins in a few microseconds after the
BST-to-HS voltage exceeds UVLO
BST
. In the two-switch
forward topology, the BST capacitor takes some time (a
few hundred microseconds) to charge and increase its
voltage above UVLO
BST
.
The typical hysteresis for both UVLO thresholds is 0.5V.
The bootstrap capacitor value should be selected care-
fully to avoid unintentional oscillations during turn-on
and turn-off at the DH output. Choose the capacitor
value about 20 times higher than the total gate capaci-
tance of the MOSFET. Use a low-ESR-type X7R dielec-
tric ceramic capacitor at BST (typically a 0.1µF ceramic
is adequate) and a parallel combination of 1µF and
0.1µF ceramic capacitors from V
DD
to GND
(MAX5062_, MAX5063_) or to PGND (MAX5064_). The
high-side MOSFET’s continuous on-time is limited due
to the charge loss from the high-side driver’s quiescent
current. The maximum on-time is dependent on the size
of C
BST
, I
BST
(50µA max), and UVLO
BST
.
Output Driver
The MAX5062/MAX5063/MAX5064 have low 2.5Ω
R
DS_ON
p-channel and n-channel devices (totem pole)
in the output stage. This allows for a fast turn-on and
turn-off of the high gate-charge switching MOSFETs.
The peak source and sink current is typically 2A.
Propagation delays from the logic inputs to the driver
outputs are matched to within 8ns. The internal p- and
n-channel MOSFETs have a 1ns break-before-make
logic to avoid any cross conduction between them. This
internal break-before-make logic eliminates shoot-
through currents reducing the operating supply current
as well as the spikes at V
DD
. The DL voltage is approxi-
mately equal to V
DD
and the DH-to-HS voltage, a diode
drop below V
DD
, when they are in a high state and to
zero when in a low state. The driver R
DS_ON
is lower at
higher V
DD
. Lower R
DS_ON
means higher source and
sink currents and faster switching speeds.
Internal Bootstrap Diode
An internal diode connects from V
DD
to BST and is
used in conjunction with a bootstrap capacitor external-
ly connected between BST and HS. The diode charges
the capacitor from V
DD
when the DL low-side switch is
on and isolates V
DD
when HS is pulled high as the high-
side driver turns on (see the Typical Operating Circuit).
The internal bootstrap diode has a typical forward volt-
age drop of 0.9V and has a 10ns typical turn-off/turn-on
time. For lower voltage drops from V
DD
to BST, connect
an external Schottky diode between V
DD
and BST.
Programmable Break-Before-Make
(MAX5064)
Half-bridge and synchronous buck topologies require
that the high- or low-side switch be turned off before
the other switch is turned on to avoid shoot-through
currents. Shoot-through occurs when both high- and
low-side switches are on at the same time. This condi-
tion is caused by the mismatch in the propagation
delay from IN_H/IN_L to DH/DL, driver output imped-
ance, and the MOSFET gate capacitance. Shoot-
through currents increase power dissipation, radiate
EMI, and can be catastrophic, especially with high
input voltages.
The MAX5064 offers a break-before-make (BBM) fea-
ture that allows the adjustment of the delay from the
input to the output of each driver. The propagation
delay from the rising edges of IN_H and IN_L to the ris-
ing edges of DH and DL, respectively, can be pro-
grammed from 16ns to 95ns. Note that the BBM time
(t
BBM
) has a higher percentage error at lower value
because of the fixed comparator delay in the BBM
block. The propagation delay mismatch (t
MATCH_
)
needs to be included when calculating the total t
BBM
error. The low 8ns (maximum) delay mismatch reduces
the total t
BBM
variation. Use the following equations to
calculate R
BBM
for the required BBM time and
t
BBM_ERROR
:
where t
BBM
is in nanoseconds.
The voltage at BBM is regulated to 1.3V. The BBM circuit
adjusts t
BBM
depending on the current drawn by R
BBM
.
Bypass BBM to AGND with a 1nF or smaller ceramic
capacitor (C
BBM
) to avoid any effect of ground bounce
caused during switching. The charging time of C
BBM
does not affect t
BBM
at turn-on because the BBM voltage
is stabilized before the UVLO clears the device turn-on.
