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ICS558AG-02LNT

P1-P3P4-P6
DATASHEET
LVHSTL TO CMOS CLOCK DIVIDER ICS558A-02
IDT™
LVHSTL TO CMOS CLOCK DIVIDER 1
ICS558A-02 REV D 051310
Description
The ICS558A-02 accepts a high-speed LVHSTL input and
provides four CMOS low skew outputs from a selectable
internal divider (divide by 3, divide by 4). The four outputs
are split into two banks of two outputs. Each bank has a
separate output enable to tri-state the output buffers.
The ICS558A-02 is a member of the IDT Clock Blocks
TM
family of clock generation, synchronization, and distribution
devices.
Features
• 16-pin TSSOP package
• LVHSTL inputs
• Accepts up to 250 MHz input frequency
• Four low skew (<250 ps) outputs
• Selectable internal divider of 3 or 4
• Operating voltage of 3.3 V
• Lead-free, RoHS compliant package
Block Diagram
OE1
CLK1
CLK2
CLK3
CLK4
HCLK
Output Divide
/3 or /4
HCLK
SEL
GND
VDD OE0
4
3
ICS558A-02
LVHSTL TO CMOS CLOCK DIVIDER LVHSTL CLOCK DIVIDER
IDT™
LVHSTL TO CMOS CLOCK DIVIDER 2
ICS558A-02 REV D 051310
Pin Assignment
Tri-State Table
Output Divide Selection
Pin Descriptions
12
1
11
2
10
3
9
SEL
4
VDD
5
VDD
6
VDD
7
HCLK
8
HCLK
CLK1
CLK2
CLK3
GND
CLK4
OE1
GND GND
16
15
14
13
OE0
VDD
16 Pin 173 Mil (0.65mm) TSSOP
OE1 OE0 CLK 1, CLK 2 CLK 3, CLK 4
0 0 Tri-state Tri-state
0 1 Clock ON Tri-state
10 Tri-state Clock ON
1 1 Clock ON Clock ON
SEL Output Divide
0/3
1/4
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 SEL Input Select pin for output divider. See table above. Internal pull-up to VDD.
2 VDD Power Connect to +3.3 V.
3 VDD Power Connect to +3.3 V.
4 HCLK Input Differential LVHSTL input (true input).
5 HCLK
Input Differential LVHSTL input (complimentary input).
6 GND Power Connect to ground.
7 GND Power Connect to ground.
8 OE0 Input Output enable for CLK1 and CLK2. See table above. Internal pull-up
to VDD.
9 OE1 Input Output enable for CLK3 and CLK4. See table above. Internal pull-up
to VDD.
10 GND Power Connect to ground.
11 CLK4 Output Low skew clock output.
12 CLK3 Output Low skew clock output.
13 CLK2 Output Low skew clock output.
14 CLK1 Output Low skew clock output.
15 VDD Power Connect to +3.3 V.
16 VDD Power Connect to +3.3 V.
ICS558A-02
LVHSTL TO CMOS CLOCK DIVIDER LVHSTL CLOCK DIVIDER
IDT™
LVHSTL TO CMOS CLOCK DIVIDER 3
ICS558A-02 REV D 051310
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS558A-02. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Recommended Operation Conditions
DC Electrical Characteristics
VDD=3.3 V ±5%, Ambient temperature 0 to +70° C, unless stated otherwise stated.
Item Rating
Supply Voltage 4.6 V
All Inputs and Outputs -0.5 V to VDD+0.5 V
Ambient Operating Temperature 0 to +70 ° C
Storage Temperature -65 to +150 ° C
Junction Temperature 125 ° C
Soldering Temperature 260 ° C
Parameter Min. Typ. Max. Units
Ambient Operating Temperature 0 +70 ° C
Power Supply Voltage (measured in respect to GND) +3.15 +3.3 +3.5 V
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3.135 3.3 3.465 V
Operating Supply Current IDD No load, 100 MHz 60 mA
Input High Voltage V
IH
OE pins VDD-0.5 VDD V
Input Low Voltage V
IL
OE pins 0.5 V
Input High Voltage V
IH
HCLK Vx + 0.1 1.2 V
Input Low Voltage V
IL
HCLK -0.3 Vx - 0.1 V
Peak to Peak Input Voltage HCLK 0.3 1.0 V
HCLK Input Leakage
Current
I
IL
-20 20 µA
Input Common Mode
Voltage
Vx Input Common Mode 0.68 0.90 V
Output High Voltage V
OH
I
OH
= -14.5 mA 2.4 V
Output Low Voltage V
OL
I
OL
= 9.4 mA 0.4 V
Nominal Output Impedance Z
O
20 Ω
Internal Pull-up Resistor R
PU
250 kΩ
Input Capacitance C
IN
7pF
P1-P3P4-P6

ICS558AG-02LNT

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Description:
IC CLK BUFFER 1:4 250MHZ 16TSSOP
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