7
Biasing and Operation
Recommended quiescent DC bias condition for optimum
power and linearity performances is Vd=5 volts with
Vg (-1.1V) set for Id=650 mA. Minor improvements in
performance are possible depending on the application.
The drain bias voltage range is 3 to 5V. A single DC gate
supply connected to Vg will bias all gain stages. Muting
can be accomplished by setting Vg to the pinch-o volt-
age Vp.
A simplied schematic for the AMMP6430 MMIC die
is shown in Figure 12. The MMIC die contains ESD and
over voltage protection diodes for Vg, and Vd terminals.
The package diagram for the recommended assembly
is shown in Figure 13. In nalized package form, ESD
diodes protect all possible ESD or over voltage damages
between Vgg and ground, Vg and Vd, Vd and ground.
Typical ESD diode current versus diode voltage for 11-
connected diodes in series is shown in Figure 14. Under
the recommended DC quiescent biasing condition
at Vds=5V, Ids=650mA, Vg=-1V, typical gate terminal
current is approximately 0.3mA. If an active biasing
technique is selected for the AMMP6430 MMIC PA DC
biasing, the active biasing circuit must have more than
10-times higher internal current that the gate terminal
current.
An optional output power detector network is also
provided. The dierential voltage between the Det-Ref
and Det-Out pads can be correlated with the RF power
of
ref
VVV
−−=
det
emerging from the RF output port. The detected voltage
is given by :
where V
ref
is the voltage at the DET_R port, V
det
is a
voltage at the DET_0 port, V
ofs
and is the zero-input-
power oset voltage.
There are three methods to calculate V
ofs
:
1. V
ofs
can be measured before each detector
measurement (by removing or switching o the
power source and measuring V
ref
- V
det
). This method
gives an error due to temperature drift of less than
0.01dB/50°C.
2. V
ofs
can be measured at a single reference
temperature. The drift error will be less than 0.25dB.
3. V
ofs
can either be characterized over temperature and
stored in a lookup table, or it can be measured at two
temperatures and a linear t used to calculate V
ofs
at
any temperature. This method gives an error close to
the method #1.
The RF ports are AC coupled at the RF input to the rst
stage and the RF output of the nal stage. No ground
wired are needed since ground connections are made
with plated through-holes to the backside of the device.
d
V
g
V
Three stage 0.5W power amplifier
in
RF
out
RF
DET_O
DET_R
DQ
Figure 12. Simplied schematic for the MMIC die
