Nexperia
PUSB3F99
ESD protection for ultra high-speed interfaces
PUSB3F99 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 1 — 15 December 2017
8 / 12
V
CL
(V)
0 642
aaa-009371
2
4
6
I
PP
(A)
0
IEC 61000-4-5; t
p
= 8/20 μs; positive pulse
Figure 11. Dynamic resistance with positive clamping;
typical values
V
CL
(V)
-2.5 0-0.5-1.5 -1.0-2.0
aaa-009372
-4
-2
0
I
PP
(A)
-6
IEC 61000-4-5; t
p
= 8/20 μs; negative pulse
Figure 12. Dynamic resistance with negative clamping;
typical values
V
CL
(V)
0 1284
aaa-009373
14
I
(A)
0
2
4
6
8
10
12
t
p
= 100 ns; Transmission Line Pulse (TLP)
Figure 13. Dynamic resistance with positive clamping;
typical values
V
CL
(V)
-6 0-2-4
aaa-009374
0
I
(A)
-14
-12
-10
-8
-6
-4
-2
t
p
= 100 ns; Transmission Line Pulse (TLP)
Figure 14. Dynamic resistance with negative clamping;
typical values
The device uses an advanced clamping structure showing a negative dynamic
resistance. This snap-back behavior strongly reduces the clamping voltage to the system
behind the ESD protection during an ESD event. Do not connect unlimited DC current
sources to the data lines to avoid keeping the ESD protection device in snap-back state
after exceeding breakdown voltage (due to an ESD pulse for instance).
