Data Sheet SSM2537
Rev. 0 | Page 3 of 16
SPECIFICATIONS
PVDD = 5.0 V, VDD = 1.8 V, f
S
= 128×, T
A
= 25°C, R
L
= 8 Ω + 33 µH, unless otherwise noted. When f
S
= 128×, PDM clock = 6.144 MHz;
when f
S
= 64×, PDM clock = 3.072 MHz.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Output Power P
f = 1 kHz, BW = 20 kHz
R
= 4 Ω, THD = 1%, PVDD = 5.0 V 2.7 W
R
= 8 Ω, THD = 1%, PVDD = 5.0 V 1.4 W
R
= 4 Ω, THD = 1%, PVDD = 3.6 V 1.35 W
R
L
= 8 Ω, THD = 1%, PVDD = 3.6 V
R
= 4 Ω, THD = 1%, PVDD = 2.5 V 0.62 W
R
= 8 Ω, THD = 1%, PVDD = 2.5 V 0.35 W
R
= 4 Ω, THD = 10%, PVDD = 5.0 V 3.38 W
R
= 8 Ω, THD = 10%, PVDD = 5.0 V 1.8 W
R
= 4 Ω, THD = 10%, PVDD = 3.6 V 1.7 W
R
= 8 Ω, THD = 10%, PVDD = 3.6 V 0.93 W
R
= 4 Ω, THD = 10%, PVDD = 2.5 V 0.78 W
R
= 8 Ω, THD = 10%, PVDD = 2.5 V 0.44 W
Total Harmonic Distortion Plus Noise THD + N f = 1 kHz
P
= 100 mW into 8 Ω, PVDD = 3.6 V 0.005 %
P
= 500 mW into 8 Ω, PVDD = 3.6 V 0.015 %
P
= 1 W into 8 Ω, PVDD = 5.0 V 0.02 %
Efficiency η P
= 2 W into 4 Ω, PVDD = 5.0 V 88 %
P
= 1.4 W into 8 Ω, PVDD = 5.0 V 93 %
Average Switching Frequency f
No input 290 kHz
Closed-Loop Gain Gain −6 dBFS PDM input, BTL output, f = 1 kHz
Gain = 5.0 V 4.78 V
Differential Output Offset Voltage V
Gain = 3.6 V 0.5 mV
Low Power Mode Wake Time t
0.5 ms
Input Sampling Frequency f
f
= 64× 1.84 3.072 3.23 MHz
f
= 128× 3.68 6.144 6.46 MHz
Propagation Delay t
f
= 6.144 MHz, normal operation 35 µs
f
= 6.144 MHz, low latency operation 15 µs
POWER SUPPLY
Supply Voltage Range
Amplifier Power Supply PVDD 2.5 3.6 5.5 V
Digital Power Supply VDD 1.65 1.8 1.95 V
Power Supply Rejection Ratio PSRR
V
= 100 mV at 100 Hz 80 dB
V
= 100 mV at 1 kHz 80 dB
V
RIPPLE
= 100 mV at 10 kHz
Supply Current, H-Bridge I
Dither input, 8 Ω + 33 µH load
PVDD = 5.0 V, f
= 64× 1.4 mA
PVDD = 5.0 V, f
= 128× 1.4 mA
PVDD = 3.6 V, f
= 64× 1.1 mA
PVDD = 3.6 V, f
= 128× 1.2 mA
PVDD = 2.5 V, f
= 64× 1.0 mA
PVDD = 2.5 V, f
= 128× 1.1 mA
Standby Current PVDD = 5.0 V 2.5 µA
Power-Down Current 100 nA
