4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER 18 FEBRUARY 22, 2017
9DBL0442 / 9DBL0452 DATASHEET
Ordering Information
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“B” is the device revision designator (will not correlate with the datasheet revision).
“xxx” is a unique factory assigned number to identify a particular default configuration.
Revision History
Part / Order Number Notes Shipping Packaging Package Temperature
9DBL0442BKILF Trays 32-pin VFQFPN -40 to +85° C
9DBL0442BKILFT Tape and Reel 32-pin VFQFPN -40 to +85° C
9DBL0452BKILF Trays 32-pin VFQFPN -40 to +85° C
9DBL0452BKILFT Tape and Reel 32-pin VFQFPN -40 to +85° C
9DBL04P2BxxxKILF Trays 32-pin VFQFPN -40 to +85° C
9DBL04P2BxxxKILFT Tape and Reel 32-pin VFQFPN -40 to +85° C
100Ω
85Ω
Factory configurable.
Contact IDT for
addtional information.
Rev. Initiator Issue Date Description Page #
A RDW 5/31/2016
1. Add PCIe G1-4 Common Clock and PCIe SRIS to electrical tables
2. Update Electrical Tables to final
3. Changed '1' value in Byte 0 to indicate "Pin Control"
4. Stylistic update to block diagram
5. Minor updates to SMBus registers 0 and 1 for Readability
6. Front page text update for family consistency.
7. Removed '000' code from ordering information, updated table.
8. Minor corrections to Byte 1 [1:0] and Byte 11 [1:0]
Various
B RDW 6/14/2016
1. Electrical Table and SMBus Updates/Corrections
2. Release to final.
Various
C RDW 6/21/2016 1. Updated ESD from 2000V to 2500V 5
D RDW 11/11/2016
1. Corrected pin 32 to indicate an internal pull down resistor, not a pull up
resistor.
2, 3
E RDW 2/8/2017 Renamed datasheet to 9DBL0442 / 9DBL0452 Various
F RDW 2/22/2017 Replaced POD drawing from P3 [3.10 EPAD] to P1 [3.15 EPAD] option. 16, 17
