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NB3N200SDG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
NB3N200S
www.onsemi.com
13
Figure 15. Equivalent Input and Output Schematic Diagrams
APPLICATION INFORMATION
Receiver Input Threshold (Failsafe)
The MLVD standard defines a type 1 and type 2 receiver.
Type 1 receivers include no provisions for failsafe and have
their differential input voltage thresholds near zero volts.
Type 2 receivers have their differential input voltage
thresholds offset from zero volts to detect the absence of a
voltage difference. The impact to receiver output by the
offset input can be seen in Table 9 and Figure 16.
Table 9. RECEIVER INPUT VOLTAGE THRESHOLD REQUIREMENTS
Receiver Type Output Low Output High
Type 1 –2.4 V ≤ VID ≤ –0.05 V 0.05 V ≤ VID ≤ 2.4 V
NB3N200S
www.onsemi.com
14
Figure 16. Receiver Differential Input Voltage Showing Transition Regions by Type
Live Insertion/Glitch−Free Power Up/Down
The NB3N200 family of products provides a glitch−free
power up/down feature that prevents the M−LVDS outputs
of the device from turning on during a power up or power
down event. This is especially important in live insertion
applications, when a device is physically connected to an
M−LVDS multipoint bus and V
CC
is ramping.
While the M−LVDS interface for these devices is glitch
free on power up/down, the receiver output structure is not.
Figure 17 shows the performance of the receiver output pin,
R (CHANNEL 2), as V
CC
(CHANNEL 1) is ramped. The
glitch on the R pin is independent of the RE voltage. Any
complications or issues from this glitch are easily resolved
in power sequencing or system requirements that suspend
operation until V
CC
has reached a steady state value.
NB3N200S
www.onsemi.com
15
Figure 17. M−LVDS Receiver Output: VCC (CHANNEL 1), R Pin (CHANNEL 2)
Simplex Theory Configurations: Data flow is
unidirectional and Point−to−Point from one Driver to one
Receiver. NB3N200SDG, NB3N202SDG, NB3N204SDG,
and NB3N205SDG devices provide a high signal current
allowing long drive runs and high noise immunity. Single
terminated interconnects yield high amplitude levels.
Parallel terminated interconnects yield typical MLVDS
amplitude levels and minimizes reflections. See Figures 18
and 19. A NB3N200SDG, NB3N202SDG, NB3N204SDG,
and NB3N205SDG can be used as the driver or as a receiver.
Figure 18. Point−to−Point Simplex Single
Termination
Figure 19. Parallel−Terminated Simplex
Simplex Multidrop Theory Configurations: Data flow is
unidirectional from one Driver with one or more Receivers
and Multiple boards are required. Single terminated
interconnects yield high amplitude levels. Parallel
terminated interconnects yield typical MLVDS amplitude
levels and minimizes reflections. On the Evaluation Test
Board, Headers P1, P2, and P3 may be used as need to
interconnect transceivers to a each other or a bus. See
Figures 20 and 21. A NB3N200SDG, NB3N202SDG,
NB3N204SDG, and NB3N205SDG can be used as the
driver or as a receiver.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

NB3N200SDG

Mfr. #:
Buy NB3N200SDG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer M-LVDS DRIVER RECEIVER
Lifecycle:
New from this manufacturer.
Delivery:
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