© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 1
1 Publication Order Number:
NB3N200S/D
NB3N200S
3.3 V Differential Multipoint
Low Voltage M-LVDS Driver
Receiver
Description
The NB3N200 is a pure 3.3 V supply differential Multipoint Low
Voltage (M−LVDS) line Driver and Receiver. NB3N200S is
TIA/EIA−899 compliant. NB3N200S offers the Type 1 receiver
threshold at 0.0 V.
These devices has a Type−1 receiver that detect the bus state with as
little as 50 mV of differential input voltage over a common−mode
voltage range of −1 V to 3.4 V. The Type−1 receivers have near zero
thresholds (±50 mV) and exhibit 25 mV of differential input voltage
hysteresis to prevent output oscillations with slowly changing signals
or loss of input.
NB3N200S supports Simplex or Half Duplex bus configurations.
Features
Low−Voltage Differential 30 W to 55 W Line Drivers and Receivers
for Signaling Rates Up to 200 Mbps
Type−1 Receivers Incorporate 25 mV of Hysteresis
Meets or Exceeds the M−LVDS Standard TIA/EIA−899
for Multipoint Data Interchange
Controlled Driver Output Voltage Transition Times for
Improved Signal Quality
−1 V to 3.4 V Common−Mode Voltage Range Allows
Data Transfer With up to 2 V of Ground Noise
Bus Pins High Impedance When Disabled or V
CC
1.5 V
M−LVDS Bus Power Up/Down Glitch Free
Operating range: V
CC
= 3.3 ±10% V( 3.0 to 3.6 V)
Operation from –40°C to 85°C.
Pb−Free SOIC 8 Package
These are Pb−Free Devices
Applications
Low−Power High−Speed Short−Reach Alternative to
TIA/EIA−485
Backplane or Cabled Multipoint Data and Clock
Transmission
Cellular Base Stations
Central−Office Switches
Network Switches and Routers
Figure 1. Logic Diagrams
MARKING
DIAGRAM
www.onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
ORDERING INFORMATION
SOIC−8
D SUFFIX
CASE 751
1
8
NB20x
AYWW
G
1
8
NB20x = Specific Device Code
x = 0, 2, 4, 5
A = Assembly Location
Y = Year
WW = Work Week
G or G = Pb−Free Package
NB3N200S
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2
B
GND
V
CC
DE A
RE
D
R
1
2
3
4
8
7
6
5
Figure 2. Pinout Diagrams (Top View)
NB3N200S
SOIC−8
Table 1. PIN DESCRIPTION SOIC−8
Number Name I/O Type Open Default Description
1 R LVCMOS Output Receiver Output Pin
2 RE LVCMOS Input High Receiver Enable Input Pin (LOW = Active, HIGH = High Z
Output)
3 DE LVCMOS Input Low Driver Enable Input Pin (LOW = High Z Output, HIGH = Active)
4 D LVCMOS Input Driver Output Pin
5 GND Ground Supply pin. Pin must be externally connected to power
supply to guarantee proper operation.
6 A M−LVDS Input /
Output
Transceiver Invert Input / Output Pin
7 B M−LVDS Input /
Output
Transceiver True Input / Output Pin
8 VCC Power Supply pin. Pin must be externally connected to power
supply to guarantee proper operation.
Table 2. DEVICE FUNCTION TABLE
TYPE 1 Receiver (NB3N200)
Inputs Output
V
ID
= V
A
− V
B
RE R
V
ID
w 50 mV L H
−50 mV < V
ID
< 50 mV L ?
V
ID
−50 mV L L
X H Z
X Open Z
Open L ?
DRIVER
Input Enable Output
D DE A / Y B / Z
L H L H
H H H L
Open H L H
X Open Z Z
X L Z Z
H = High, L = Low, Z = High Impedance, X = Don’t Care, ? = Indeterminate
NB3N200S
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3
Table 3. ATTRIBUTES (Note 1)
Characteristics
Value
Internal Input Pullup Resistor
50 kW
Internal Input Pulldown Resistor
50 kW
ESD
Protection
Human Body Model (JEDEC
Standard 22, Method A114−A)
A, B, Y, Z
All Pins
±6 kV
±2 kV
Machine Model All Pins ±200 V
Charged –Device Model (JEDEC
Standard 22, Method C101)
All Pins ±1500 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1
Flammability Rating
Oxygen Index
UL−94 V−0 @ 0.125 in
28 to 34
Transistor Count 917 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 2)
Symbol
Parameter Condition 1 Condition 2 Rating Unit
V
CC
Supply Voltage −0.5 V
CC
4.0 V
V
IN
Input Voltage
D, DE, RE −0.5 V
IN
4.0
V
A, B (200, 204) −1.8 V
IN
4.0
A, B (202, 205) −4.0 V
IN
6.0
I
OUT
Output Voltage R
Y, Z, A, B
−0.3 I
OUT
4.0
−1.8 I
OUT
4.0
V
T
A
Operating Temperature Range, Industrial −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
θ
JA
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
SOIC−8 190
130
°C/W
°C/W
θ
JC
Thermal Resistance (Junction−to−Case) (Note 3) SOIC−8 41 to 44 °C/W
T
sol
Wave Solder 265 °C
P
D
Power Dissipation (Continuous) SOIC−8 T
A
= 25°C
25°C < T
A
< 85°C
T
A
= 85°C
725
5.8
377
mW
mW/°C
mW
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 5. DC CHARACTERISTICS VCC = 3.3 ±10% V( 3.0 to 3.6 V), GND = 0 V, T
A
= −40°C to +85°C (See Notes 4, 5)
Symbol Characteristic Min Typ Max Unit
ICC Power Supply Current
Receiver Disabled Driver Enabled RE
and DE at V
CC
, R
L
= 50 W, All others open
Driver and Receiver Disabled RE at VCC, DE at 0 V, R
L
= No Load, All others open
Driver and Receiver Enabled RE at 0 V, DE at V
CC
, R
L
= 50 W, All others open
Receiver Enabled Driver Disabled RE at 0 V, DE at 0 V, R
L
= 50 W, All others open
13
1
16
22
4
24
13
mA
V
IH
Input HIGH Voltage 2 V
CC
V
V
IL
Input LOW Voltage GND 0.8 V
VBUS Voltage at any bus terminal VA, VB, VY or VZ −1.4 3.8 V
|VID| Magnitude of differential input voltage 0.05 V
CC
DRIVER

NB3N200SDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer M-LVDS DRIVER RECEIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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