PCA9546A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 6 — 30 April 2014 7 of 30
NXP Semiconductors
PCA9546A
4-channel I
2
C-bus switch with reset
6.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of t
w(rst)L
, the PCA9546A resets its
registers and I
2
C-bus state machine and deselects all channels. The RESET input must
be connected to V
DD
through a pull-up resistor.
6.4 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9546A in
a reset condition until V
DD
has reached V
POR
. At this point, the reset condition is released
and the PCA9546A registers and I
2
C-bus state machine are initialized to their default
states (all zeroes) causing all the channels to be deselected. Thereafter, V
DD
must be
lowered below 0.2 V for at least 5 s in order to reset the device.
6.5 Voltage translation
The pass gate transistors of the PCA9546A are constructed such that the V
DD
voltage can
be used to limit the maximum voltage that is passed from one I
2
C-bus to another.
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 11 “
Static characteristics” of this data
sheet). In order for the PCA9546A to act as a voltage translator, the V
o(sw)
voltage should
be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then V
o(sw)
should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 7
, we see that V
o(sw)(max)
is at 2.7 V when the PCA9546A supply voltage is 3.5 V or
lower, so the PCA9546A supply voltage could be set to 3.3 V. Pull-up resistors can then
be used to bring the bus voltages to their appropriate levels (see Figure 14
).
(1) maximum
(2) typical
(3) minimum
Fig 7. Pass gate voltage versus supply voltage
9
''
9
DDD
9
RVZ
9
