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NLAS4053DTG

P1-P3P4-P6P7-P9P10-P12P13-P14
© Semiconductor Components Industries, LLC, 2011
March, 2011 − Rev. 3
1 Publication Order Number:
NLAS4053/D
NLAS4053
Analog Multiplexer/
Demultiplexer
Triple 2:1 Analog Switch−Multiplexer
Improved Process, Sub−Micron Silicon
Gate CMOS
The NLAS4053 is an improved version of the MC14053 and
MC74HC4053 fabricated in sub−micron Silicon Gate CMOS
technology for lower R
DS(on)
resistance and improved linearity with
low current. This device may be operated either with a single supply or
dual supply up to ±3.0 V to pass a 6 V
PP
signal without coupling
capacitors.
When operating in single supply mode, it is only necessary to tie
V
EE
, pin 7 to ground. For dual supply operation, V
EE
is tied to a
negative voltage, not to exceed maximum ratings. Pin for pin
compatible with all industry standard versions of ‘4053.’
Features
• Improved R
DS(on)
Specifications
• Pin for Pin Replacement for MAX4053 and MAX4053A
− One Half the Resistance Operating at 5.0 Volts
• Single or Dual Supply Operation
− Single 3−5 Volt Operation, or Dual ±3.0 Volt Operation
− With V
CC
of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
− No Translators Needed
− Address and Inhibit Pins are Over−Voltage Tolerant and May Be
− Driven Up +6.0 V Regardless of V
CC
− Greatly Improved Noise Margin Over MAX4053 and MAX4053A
• Improved Linearity Over Standard HC4053 Devices
• Popular SOIC and the Space Saving TSSOP Packages
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
TSSOP−16
DT SUFFIX
CASE 948F
SOIC−16
D SUFFIX
CASE 751B
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
NLAS4053G
AWLYWW
NLAS
4053
ALYWG
G
1
16
1
16
A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)
NLAS4053
http://onsemi.com
2
Figure 1. Pin Connection
(Top View)
Figure 2. Logic Diagram
1516 14 13 12 11 10
21 34567
V
CC
9
8
COM
B
COM
C
NO
C
NC
C
Add
C
Add
B
Add
A
NO
B
NC
B
NO
A
COM
A
NC
A
Inhibit V
EE
GND
COM
B
COM
C
NO
C
NC
C
C
B
A
NO
B
NC
B
NO
A
COM
A
NC
A
Enable
TRUTH TABLE
Inhibit
Address
ON SWITCHES*
C B A
1 X
don’t care
X
don’t care
X
don’t care
All switches open
0 0 0 0 COM
A
−NC
A
,
COM
B
−NC
B
,
COM
C
−NC
C
0 0 0 1 COM
A
−NO
A
,
COM
B
−NC
B
,
COM
C
−NC
C
0 0 1 0 COM
A
−NC
A
,
COM
B
−NO
B
,
COM
C
−NC
C
0 0 1 1 COM
A
−NO
A
,
COM
B
−NO
B
,
COM
C
−NC
C
0 1 0 0 COM
A
−NC
A
,
COM
B
−NC
B
,
COM
C
−NO
C
0 1 0 1 COM
A
−NO
A
,
COM
B
−NC
B
,
COM
C
−NO
C
0 1 1 0 COM
A
−NC
A
,
COM
B
−NO
B
,
COM
C
−NO
C
0 1 1 1 COM
A
−NO
A
,
COM
B
−NO
B
,
COM
C
−NO
C
*NO, NC, and COM pins are identical and interchangeable. Either may be
considered an input or output; signals pass equally well in either direction.
NLAS4053
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
EE
Negative DC Supply Voltage (Referenced to GND) −7.0 to 0.5 V
V
CC
Positive DC Supply Voltage (Note 1) (Referenced to GND)
(Referenced to V
EE
)
−0.5 to 7.0
−0.5 to 7.0
V
V
IS
Analog Input Voltage V
EE
−0.5 to V
CC
0.5 V
V
IN
Digital Input Voltage (Referenced to GND) −0.5 to 7.0 V
I DC Current, Into or Out of Any Pin 50 mA
T
STG
Storage Temperature Range −65 to 150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260
_C
T
J
Junction Temperature under Bias 150
_C
JA
Thermal Resistance SOIC
TSSOP
143
164
°C/W
P
D
Power Dissipation in Still Air, SOIC
TSSOP
500
450
mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
2000
200
1000
V
I
LATCHUP
Latchup Performance Above V
CC
and Below GND at 125°C (Note 5) 300 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The absolute value of V
CC
|V
EE
| ≤ 7.0.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
EE
Negative DC Supply Voltage (Referenced to GND) −5.5 GND V
V
CC
Positive DC Supply Voltage (Referenced to GND)
(Referenced to V
EE
)
2.5
2.5
5.5
6.6
V
V
IS
Analog Input Voltage V
EE
V
CC
V
V
IN
Digital Input Voltage (Note 6) (Referenced to GND) 0 5.5 V
T
A
Operating Temperature Range, All Package Types −55 125
_C
t
r
, t
f
Input Rise/Fall Time V
CC
= 3.0 V 0.3 V
(Channel Select or Enable Inputs) V
CC
= 5.0 V 0.5 V
0
0
100
20
ns/V
6. Unused digital inputs may not be left open. All digital inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
P1-P3P4-P6P7-P9P10-P12P13-P14

NLAS4053DTG

Mfr. #:
Buy NLAS4053DTG
Manufacturer:
ON Semiconductor
Description:
Multiplexer Switch ICs LOG ANALOG SWITCH
Lifecycle:
New from this manufacturer.
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