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ID82C82

P1-P3P4-P6P7-P9
274
August 25, 2015
82C82
CMOS Octal Latching Bus Driver
Features
• Full Eight-Bit Parallel Latching Buffer
• Bipolar 8282 Compatible
• Three-State Noninverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
• Gated Inputs:
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10A
• Operating Temperature Ranges
- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . . 0
o
C to +70
o
C
- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to +85
o
C
- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Description
The Intersil 82C82 is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon
gate CMOS process (Scaled SAJI IV). The 82C82 provides
an eight-bit parallel latch/buffer in a 20 pin package. The
active high strobe (STB) input allows transparent transfer of
data and latches data on the negative transition of this sig-
nal. The active low output enable (OE
) permits simple inter-
face to state-of-the-art microprocessor systems.
Pinouts
82C82 (PDIP, CERDIP)
TOP VIEW
82C82 (PLCC, CLCC)
TOP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
7
DI
6
OE
GND
V
CC
DO
1
DO
2
DO
3
DO
0
DO
4
DO
5
DO
6
DO
7
STB
193 2 201
15
16
17
18
14
9
10 11 12 13
4
5
6
7
8
DI
4
DI
5
DI
6
DI
7
DI
3
OE
GND
STB
DO
7
DO
6
DO
2
DO
3
DO
4
DO
5
DO
1
DI
2
DI
1
DI
0
V
CC
DO
0
N
O
L
O
N
G
E
R
A
V
A
I
L
A
B
L
E
O
R
S
U
P
P
O
R
T
E
D
TRUTH TABLE
STB OE DI DO
XHXHi-Z
HLLL
HLHH
LX †
H = Logic One
L = Logic Zero
X = Don’t Care
† = Latched to Value of Last
Data
Hi-Z = High Impedance
= Neg. Transition
PIN NAMES
PIN DESCRIPTION
DI
0
-DI
7
Data Input Pins
DO
0
-DO
7
Data Output Pins
STB Active High Strobe
OE
Active Low Output
Enable
FN2975.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
| Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas LLC 2002, 2015. All Rights Reserved
275
Functional Diagram
Gated Inputs
During normal system operation of a latch, signals on the bus
at the device inputs will become high impedance or make
transitions unrelated to the operation of the latch. These unre-
lated input transitions switch the input circuitry and typically
cause an increase in power dissipation in CMOS devices by
creating a low resistance path between V
CC
and GND when
the signal is at or near the input switching threshold. Addition-
ally, if the driving signal becomes high impedance (“float” con-
dition), it could create an indeterminate logic state at the input
and cause a disruption in device operation.
The Intersil 82C8X Series of bus drivers eliminates these con-
ditions by turning off data inputs when data is latched (STB =
logic zero for the 82C82/83H) and when the device is disabled
(OE = logic one for 82C86H/87H). These gated inputs dis-
connect the input circuitry from the V
CC
and ground power
supply pins by turning off the upper P-channel and lower N-
channel (see Figures 1, 2). No new current flow from V
CC
to
GND occurs during input transitions and invalid logic states
from floating inputs are not transmitted. The next stage is held
to a valid logic level internal to the device.
Ordering Information
PART NUMBER TEMP. RANGE PACKAGE PKG. NO.
CP82C82
(No longer available)
0
o
C to +70
o
C 20 Ld PDIP E20.3
IP82C82 (No longer available) -40
o
C to +85
o
C
CS82C82 (No longer available) 0
o
C to +70
o
C 20 Ld PLCC N20.35
IS82C82 (No longer available) -40
o
C to +85
o
C
CD82C82 (No longer available) 0
o
C to +70
o
C 20 Ld CERDIP F20.3
ID82C82 (No longer available) -40
o
C to +85
o
C
MD82C82/B (No longer available) -55
o
C to +125
o
C
8406701RA SMD #
MR82C82/B (No longer available) -55
o
C to +125
o
C 20 Pad CLCC J20.A
84067012A(No longer available) SMD #
DI
O
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
OE
STB
DQ
CLK
82C82
276
DC input voltage levels can also cause an increase in ICC if
these input levels approach the minimum V
IH
or maximum
V
IL
conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans
parent mode (STB = logic one). ICC remains below the max-
imum ICC standby specification of l0mA during the time
inputs are disabled, thereby, greatly reducing the average
power dissipation of the 82C8X series devices
Typical 82C82 System Example
In a typical 80C86/88 system, the 82C82 is used to latch
multiplexed addresses and the STB input is driven by ALE
(Address Latch Enable) (see Figure 3). The high pulse width
of ALE is approximately 100ns with a bus cycle time of
800ns (80C86/88 at 5MHz). The 82C82 inputs are active
only 12.5% of the bus cycle time. Average power dissipation
related to input transitioning is reduced by this factor also.
Application Information
Decoupling Capacitors
The transient current required to charge and discharge the 300pF load capacitance specified in the 82C82 data sheet is
FIGURE 16. 82C82/83H FIGURE 17. 82C86H/87H GATED INPUTS
P
P
P
N
N
N
STB
DATA IN
INTERNAL
DATA
V
CC
V
CC
P
P
N
N
OE
DATA IN
INTERNAL
DATA
V
CC
P
N
V
CC
82C82
P1-P3P4-P6P7-P9

ID82C82

Mfr. #:
Buy ID82C82
Manufacturer:
Renesas / Intersil
Description:
Latches 20 CDIP -40+85C 5 0V 32NS OCTL BUS TRANSC
Lifecycle:
New from this manufacturer.
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