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2N5087TA

P1-P3P4-P6P7-P9P10-P12
Product Specifications
PART NO.:
VL47B5663A-F8SE-I
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – ww w.virtium.com 4
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VDD
Voltage on VDD pin relative to VSS
-0.4
1.975
V
VDDQ
Voltage on VDDQ pin relative to VSS
-0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
-0.4
1.975
V
TSTG
Storage temperature
-55
100
0
C
IL
Input leakage current; Any input 0V<VIN<VDD;
VREF input 0V<VIN<0.95V;
Other pins not under test = 0V
Address, RAS#,
CAS#, WE#, BA
-32
32
uA
CS#, CKE, ODT,
CK, CK#
-16
16
uA
DM
-4
4
uA
IOZ
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT are disabled
DQ, DQS, DQS#
-10
10
uA
IVREF
VREF supply leakage current; VREF = Valid VREF level
-16
16
uA
DC Operating Conditions
Symbol
Parameter
Min
Typical
Max
Unit
Notes
VDD
Supply Voltage
1.425
1.5
1.575
V
1,2
VDDQ
I/O Supply Voltage
1.425
1.5
1.575
V
1,2
VREFDQ (DC)
I/O reference voltage DQ bus
0.49 x VDD
0.5 x VDD
0.51 x VDD
V
3,4
VREFCA (DC)
Input reference voltage CMD/ADD bus
0.49 x VDD
0.5 x VDD
0.51 x VDD
V
3,4
VTT
Termination Reference Voltage
-0.483 x VDDQ
0.5 x VDDQ
+0.517 x VDDQ
V
5
Notes:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/-1% VDD
4. For reference: approximate VDD/2 +/-15mV.
5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals’ voltage margin and will reduce
timing margins.
Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating temperature
-40 to +95
0
C
1,2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JEDEC JESD51-2.
2. At -40 to +85
o
C, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
85
o
C < TOPER <= 95
o
C.
Product Specifications
PART NO.:
VL47B5663A-F8SE-I
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – ww w.virtium.com 5
Input DC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Unit
Command and Address
VIHCA(DC)
Input High (Logic 1) Voltage
VREF + 0.100
VDD
V
VILCA(DC)
Input Low (Logic 0) Voltage
VSS
VREF - 0.100
V
DQ and DM
VIHDQ(DC)
Input High (Logic 1) Voltage
VREF + 0.100
VDD
V
VILDQ(DC)
Input Low (Logic 0) Voltage
VSS
VREF - 0.100
V
Input AC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Unit
Command and Address
VIHCA(AC)
Input High (Logic 1) Voltage
VREF + 0.175
-
V
VILCA(AC)
Input Low (Logic 0) Voltage
-
VREF - 0.175
V
DQ and DM
VIHDQ(AC)
Input High (Logic 1) Voltage
VREF + 0.175
-
V
VILDQ(AC)
Input Low (Logic 0) Voltage
-
VREF - 0.175
V
Input/Output Capacitance
TA=25
0
C, f=100MHz
Parameter
Symbol
F8
(DDR3-1066)
Unit
Min
Max
Input capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#)
CIN1
16
28
pF
Input capacitance (CKE0, CKE1), (ODT0, ODT1), (CS0#, CS1#)
CIN2
10
16
pF
Input capacitance (CK0, CK0#), (CK1, CK1#)
CIN3
10.4
16.8
pF
Input/Output capacitance (DQ, DQS, DQS#, DM)
CIO
7
9.4
pF
Product Specifications
PART NO.:
VL47B5663A-F8SE-I
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – ww w.virtium.com 6
IDD Specification
Condition
Symbol
F8
(DDR3-1066)
Unit
Operating one bank active-precharge current;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
IDD0*
560
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC= tRC(IDD);
tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W.
IDD1*
680
mA
Precharge power-down current;
All device banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
IDD2P-F**
400
mA
IDD2P-S**
160
mA
Precharge standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control
and address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD2N**
480
mA
Precharge quiet standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2Q**
480
mA
Active power-down current;
All device banks open; tCK= tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING.
IDD3P**
400
mA
Active standby current;
All device banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS MAX(IDD));
CKE is HIGH, CS# is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD3N**
720
mA
Operating burst read current;
All device banks open; Continuous burst reads; IOUT = 0mA; BL = 8; CL =
CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W.
IDD4R*
960
mA
Operating burst write current;
All device banks open; Continuous burst writes; BL = 8; CL = CL(IDD); AL = 0;
tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING.
IDD4W*
1000
mA
Burst refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH;
CS# is HIGH between valid commands; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING.
IDD5**
2400
mA
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING.
IDD6**
160
mA
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL = tRCD(IDD)
- 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD =
1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between valid commands; Address bus
inputs are STABLE during DESELECTs; Data pattern is same as IDD4R.
IDD7*
1560
mA
Note: IDD specification is based on Samsung E-die components.
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
P1-P3P4-P6P7-P9P10-P12

2N5087TA

Mfr. #:
Buy 2N5087TA
Manufacturer:
ON Semiconductor / Fairchild
Description:
Bipolar Transistors - BJT PNP Transistor General Purpose
Lifecycle:
New from this manufacturer.
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