CY7C1019CV33
1 Mbit (128K x 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05130 Rev. *G Revised September 08, 2009
Features
■ Temperature Ranges
❐ Industrial: –40°C to 85°C
❐ Automotive-A: –40°C to 85°C
■ Pin and Function compatible with CY7C1019BV33
■ High Speed
❐ t
AA
= 10 ns
■ CMOS for optimum Speed and Power
■ Data Retention at 2.0V
■ Center Power/Ground Pinout
■ Automatic Power Down when deselected
■ Easy Memory Expansion with CE
and OE Options
■ Available in Pb-free and non Pb-free 48-Ball VFBGA, 32-Pin
TSOP II and 400-mil SOJ Package
Functional Description
The CY7C1019CV33 is a high performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE
), an active LOW
Output Enable (OE
), and tristate drivers. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE
)
and Write Enable (WE
) inputs LOW. Data on the eight I/O pins
(I/O
0
through I/O
7
) is then written into the location specified on
the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip Enable
(CE
) and Output Enable (OE) LOW while forcing Write Enable
(WE
) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high impedance state when the device is deselected (CE
HIGH),
the outputs are disabled (OE
HIGH), or during a write operation
(CE
LOW, and WE LOW).
14
15
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
128K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
A
10
CE
A
A
16
A
9
Logic Block Diagram
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