LT1468
11
1468fb
APPLICATIONS INFORMATION
Input Considerations
Each input of the LT1468 is protected with a 100 series
resistor and back-to-back diodes across the bases of the
input devices. If the inputs can be pulled apart, the input
current should be limited to less than 10mA with an ex-
ternal series resistor. Each input also has two ESD clamp
diodes—one to each supply. If an input is driven above
the supply, limit the current with an external resistor to
less than 10mA.
The LT1468 employs bias current cancellation at the inputs.
The inverting input current is trimmed at zero common
mode voltage to minimize errors in inverting applications
such as I-to-V converters. The noninverting input current
is not trimmed and has a wider variation and therefore a
larger maximum value. As the input offset current can be
greater than either input current, the use of balanced source
resistance is NOT recommended as it actually degrades
DC accuracy and also increases noise.
The input bias currents vary with common mode voltage
as shown in the Typical Performance Characteristics.
The cancellation circuitry was not designed to track this
common mode voltage because the settling time would
have been adversely affected.
The LT1468 inputs can be driven to the negative supply
and to within 0.5V of the positive supply without phase
reversal. As the input moves closer than 0.5V to the posi-
tive supply, the output reverses phase.
Input Stage Protection
R1
100Ω
R2
100Ω
+IN –IN
1468 AI03
Q1 Q2
Total Input Noise
The curve of Total Noise vs Unmatched Source Resistance
in the Typical Performance Characteristics shows that
with source resistance below 1k, the voltage noise of the
amplifi er dominates. In the 1k to 20k region the increase
in noise is due to the source resistance. Above 20k the
input current noise component is larger than the resistor
noise.
Capacitive Loading
The LT1468 drives capacitive loads of up to 100pF in unity
gain and 300pF in a gain of –1. When there is a need to
drive a larger capacitive load, a small series resistor should
be inserted between the output and the load. In addition,
a capacitor should be added between the output and the
inverting input as shown in Driving Capacitive Loads.
Settling Time
The LT1468 is a single stage amplifi er with an optimal
thermal layout that leads to outstanding settling
performance. Measuring settling, even at the 12-bit level
is very challenging, and at the 16-bit level requires a great
deal of subtlety and expertise. Fortunately, there are two
excellent Linear Technology reference sources for settling
measurements, Application Notes 47 and 74. Appendix B
of AN47 is a vital primer on 12-bit settling measurements,
and AN74 extends the state of the art while concentrating
on settling time with a 16-bit current output DAC input.
Driving Capacitive Loads
–
+
LT1468
1468 AI04
R
G
R
O
R
F
C
F
C
L
V
IN
V
OUT
R
O
≥ (1 + R
F
/R
G
)/(2πC
L
5MHz)
R
F
≥ 10R
O
C
F
= (2R
O
/R
F
)C
L
