DF2S6P2CTC,L3F Datasheet DF2S6P2CTC,L3F | P1-P3

DF2S6P2CTC

1

ESD Protection Diodes Silicon Epitaxial Planar

DF2S6P2CTC

Start of commercial production

2018-04

1.

1. General

General

The DF2S6P2CTC is a TVS diode (ESD protection diode) protects semiconductor devices used in mobile device

interfaces and other applications to protect against static electricity and noise.

The DF2S6P2CTC has realized high I

PP

, in order to protect a semiconductor devices from the indirect lightning

stroke and the transition voltage (at the time of power activation).

Furthermore, the DF2S6P2CTC is housed in an ultra-compact package (1.6 mm × 0.8 mm) to meet applications

that require a small footprint.

2.

2. Applications

Applications

Mobile Equipment

 Smartphones

 Tablets

 Notebook PCs

Desktop PCs

Note: This product is designed for protection against electrostatic discharge (ESD) and is not intended for any other

purpose, including, but not limited to, voltage regulation.

3.

3. Features

Features

(1) Suitable for use with a 5.0 V signal line. (V

RWM

≤ 5.5 V)

(2) Protects devices with its high ESD performance.

(V

ESD

= ±30 kV (Contact / Air) @IEC61000-4-2)

(3) Low dynamic resistance protects semiconductor devices from static electricity and noise.

(R

DYN

= 0.08 Ω (typ.))

(4) Snapback characteristics realizing low clamping voltage protects semiconductor devices.

(V

C

= 18 V@I

PP

= 80 A (typ.))

(5) Compact package is suitable for use in high density board layouts such as in mobile devices.

(1.6 mm × 0.8 mm size (Nickname: CST2C))

4.

4. Packaging

Packaging

CST2C

2018-05-09

Rev.3.0

Toshiba Electronic Devices & Storage Corporation

DF2S6P2CTC

2

5.

5. Example of Circuit Diagram

Example of Circuit Diagram

6.

6. Quick Reference Data

Quick Reference Data

Characteristics

Working peak reverse voltage

Dynamic resistance

Electrostatic discharge voltage

(IEC61000-4-2) (Contact)

Symbol

V

RWM

R

DYN

V

ESD

Note

(Note 1)

(Note 2)

(Note 3)

Test Condition



Min



Typ.



0.08



Max

5.5



30

Unit

V

Ω

kV

Note 1: Recommended operating condition.

Note 2: TLP parameters: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of

dynamic resistance using least squares fit of TLP characteristics between I

PP1

= 16 A and I

PP2

= 30 A.

Note 3: Criterion: No damage to devices.

6.1.

6.1. ESD Clamp Waveform (Note)

ESD Clamp Waveform (Note)

Fig.

Fig. 6.1.1

6.1.1

6.1.1 +8 kV

+8 kV

+8 kV Fig.

Fig.

Fig. 6.1.2

6.1.2

6.1.2 -8 kV

-8 kV

Fig.

Fig. 6.1.3

6.1.3

6.1.3 IEC61000-4-2 (Contact)

IEC61000-4-2 (Contact)

Note: The above characteristics curves are presented for reference only and not guaranteed by production test,

unless otherwise noted.

2018-05-09

Rev.3.0

Toshiba Electronic Devices & Storage Corporation

DF2S6P2CTC

3

6.2.

6.2. TLP Characteristics (Note)

TLP Characteristics (Note)

Note: The above characteristics curves are presented for reference only and not guaranteed by production test,

unless otherwise noted.

6.3.

6.3. Clamp Voltage - Peak Pulse Current (V

Clamp Voltage - Peak Pulse Current (V

C

- I

PP

) (Note)

Fig.

Fig. 6.3.1

6.3.1

6.3.1 V

V

C

- I

PP

Fig.

Fig. 6.3.2

6.3.2

6.3.2 Based on IEC61000-4-5 8/20

Based on IEC61000-4-5 8/20

Based on IEC61000-4-5 8/20 µ

µ

µs pulse.

s pulse.

Note: The above characteristics curves are presented for reference only and not guaranteed by production test,

unless otherwise noted.

2018-05-09

Rev.3.0

Toshiba Electronic Devices & Storage Corporation

DF2S6P2CTC,L3F

DF2S6P2CTC,L3F

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