© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 11
1 Publication Order Number:
NTD110N02R/D
NTD110N02R, STD110N02R
Power MOSFET
24 V, 110 A, N−Channel DPAK
Features
• Planar HD3e Process for Fast Switching Performance
• Low R
DS(on)
to Minimize Conduction Loss
• Low C
iss
to Minimize Driver Loss
• Low Gate Charge
• Optimized for High Side Switching Requirements in
High−Efficiency DC−DC Converters
• S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (T
J
= 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage V
DSS
24 V
Gate−to−Source Voltage − Continuous V
GS
±20 V
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ T
C
= 25°C
Drain Current
− Continuous @ T
C
= 25°C, Chip
− Continuous @ T
C
= 25°C
Limited by Package
− Continuous @ T
A
= 25°C
Limited by Wires
− Single Pulse (t
p
= 10 ms)
R
q
JC
P
D
I
D
I
D
I
D
I
D
1.35
110
110
110
32
110
°C/W
W
A
A
A
A
Thermal Resistance
− Junction−to−Ambient (Note 1)
− Total Power Dissipation @ T
A
= 25°C
− Drain Current − Continuous @ T
A
= 25°C
R
q
JA
P
D
I
D
52
2.88
17.5
°C/W
W
A
Thermal Resistance
− Junction−to−Ambient (Note 2)
− Total Power Dissipation @ T
A
= 25°C
− Drain Current − Continuous @ T
A
= 25°C
R
q
JA
P
D
I
D
100
1.5
12.5
°C/W
W
A
Operating and Storage Temperature Range T
J
, T
stg
−55 to
175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 50 Vdc, V
GS
= 10 Vdc,
I
L
= 15.5 Apk, L = 1.0 mH, R
G
= 25 W)
E
AS
120 mJ
Maximum Lead Temperature for Soldering
Purposes, (1/8″ from case for 10 s)
T
L
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in drain pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
http://onsemi.com
24 V
4.1 mW @ 10 V
R
DS(on)
TYP
110 A
I
D
MAXV
(BR)DSS
N−Channel
D
S
G
DPAK
CASE 369AA
(Surface Mount)
STYLE 2
1
2
3
4
MARKING DIAGRAM
& PIN ASSIGNMENT
1
Gate
3
Source
2
Drain
4
Drain
AYWW
T
110N2G
A = Assembly Location*
Y = Year
WW = Work Week
T110N2 = Device Code
G = Pb−Free Package
See detailed ordering and shipping information on page 5 o
this data sheet.
ORDERING INFORMATION
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
