ICS843156AK REVISION B May 26, 2016 9 ©2016 Integrated Device Technology, Inc.
ICS843156 Data Sheet CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
TEST_CLK Input
For applications not requiring the use of the test clock, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the TEST_CLK to ground.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
LVCMOS Control Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform ance,
power supply isolation is required. The ICS843156 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V
CC,
V
CCA
and V
CCO
should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic V
CC
pin and also shows that V
CCA
requires that an
additional 10 resistor along with a 10F bypass capacitor be
connected to the V
CCA
pin.
Figure 1. Power Supply Filtering
Crystal Input Interface
The ICS843156 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error. The optimum C1 and C2
values can be slightly adjusted for different board layouts.
Figure 2. Crystal Input Interface
V
CC
V
CCA
3.3V
10µF0.01µF
0.01µF
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
27pF
C2
27pF
