13
LTC2901
2901fb
Pull-Up Current vs V2 curve). Output rise time (10% to
90%) is estimated using:
t
RISE
≈ 2.2 • R
PU
• C
LOAD
where R
PU
is the on-resistance of the pull-up transistor.
The on-resistance as a function of the V2 voltage at room
temperature is estimated using:
R
V
PU
=Ω
610
21
5
•
–
with V2 = 3.3V, R
PU
is about 260k. Using 150pF for load
capacitance, the rise time is 86μs. If the output needs to
pull up faster and/or to a higher voltage, a smaller
external pull-up resistor may be used. Using a 10k pull-
up resistor, the rise time is reduced to 3.3μs for a 150pF
load capacitance.
The LTC2901-2 has an active pull-up to V2 on the RST
output. The typical performance curve (RST Pull-Up Cur-
rent vs V2 curve) demonstrates that the pull-up current is
somewhat linear versus the V2 voltage and R
PU
is esti-
mated to be approximately 625Ω. A 150pF load capaci-
tance makes the rise time about 206ns.
Watchdog Timer
The watchdog circuit typically monitors a μP’s activity. The
μP is required to change the logic state of the WDI pin on
a periodic basis in order to clear the watchdog timer and
prevent the WDO pin (LTC2901-1/LTC2901-2) from going
low. Whenever RST is low, the watchdog timer is cleared
and WDO is set high. The watchdog timer is started when
RST pulls high. Subsequent edges received on the WDI pin
will clear the watchdog timer. The timer will continue to
run until the watchdog timer times out. Once the watchdog
timer times out, internal circuitry will bring the WDO pin
low. WDO will remain low and the watchdog timer will
remain cleared until the next edge is received on the WDI
pin or until RST goes low.
In the LTC2901-3/LTC2901-4, there is no WDO pin. Instead,
the RST pin is pulled low for the programmed reset time-
out period whenever a WDI edge is missed. In this manner,
a full system reset can be issued after a watchdog failure.
To disable the watchdog timer, simply ground the CWT pin
(Pin 9). With CWT held at ground, any reset event will force
WDO high indefinitely. It is safe to leave the WDI pin
(Pin 8) unconnected because the weak internal pull-up
(10μA typ) will pull WDI high. Tying WDI to V1 or ground
is also allowed, but grounding the WDI pin will force the
pull-up current to be drawn continuously.
Selecting the Reset Timing Capacitor
The reset time-out period is adjustable in order to accom-
modate a variety of microprocessor applications. The
reset time-out period, t
RST
, is adjusted by connecting a
capacitor, C
RT
, between the CRT pin and ground. The
value of this capacitor is determined by:
C
RT
= t
RST
• 217 • 10
–9
with C
RT
in Farads and t
RST
in seconds. The C
RT
value per
millisecond of delay can also be expressed as C
RT
/ms =
217 (pF/ms).
Leaving the CRT pin unconnected will generate a mini-
mum reset time-out of approximately 50μs. Maximum
reset time-out is limited by the largest available low
leakage capacitor. The accuracy of the time-out period will
be affected by capacitor leakage (the nominal charging
current is 2μA) and capacitor tolerance. A low leakage
ceramic capacitor is recommended.
Selecting the Watchdog Timing Capacitor
The watchdog time-out period is adjustable and can be
optimized for software execution. The watchdog time-out
period, t
WD
, is adjusted by connecting a capacitor, C
WT
,
between the CWT pin and ground. Given a specified
watchdog time-out period, the capacitor is determined by:
C
WT
= t
WD
• 50 • 10
–9
with C
WT
in Farads and t
WD
in seconds. The C
WT
value per
millisecond of delay can also be expressed as C
WT
/ms =
50 (pF/ms).
Leaving the CWT pin unconnected will generate a mini-
mum watchdog time-out of approximately 200μs. Maxi-
mum time-out is limited by the largest available low
leakage capacitor. The accuracy of the time-out period will
be affected by capacitor leakage (the nominal charging
current is 2μA) and capacitor tolerance. A low leakage
ceramic capacitor is recommended.
APPLICATIO S I FOR ATIO
WUUU
