MAX16063TG+ Datasheet MAX16063TG+, MAX16063TG+T | P10-P12

MAX16063

1% Accurate, Low-Voltage,

Quad Window Voltage Detector

10 ______________________________________________________________________________________

Use the following formulas to calculate the error:

where E

and E

are the undervoltage and over-

voltage error (in %), respectively.

2) Calculate R3 based on R

TOTAL

and the desired

upper trip point:

3) Calculate R2 based on R

TOTAL

, R3, and the

desired lower trip point:

4) Calculate R1 based on R

TOTAL

, R3, and R2:

Overvoltage Shutdown

The MAX16063 is ideal for overvoltage-shutdown appli-

cations. Figure 3 shows a typical circuit for this applica-

tion using a pass p-channel MOSFET. The MAX16063 is

powered directly from the system voltage supply. Select

R1 and R2 to set the trip voltage. When the supply volt-

age remains below the selected threshold, a low logic

level on UVOUT_ turns on the p-channel MOSFET. In

the case of an overvoltage event, UVOUT_ goes high

turning off the MOSFET, and shuts down the power to

the load.

Figure 4 shows a similar application using a fuse and a

silicon-controlled rectifier (SCR). An overvoltage event

turns on the SCR and shorts the supply to ground. The

surge of current through the short circuit blows the fuse

and terminates the current to the load. Select R3 so that

the gate of the SCR is properly biased when UVOUT_

goes high.

Unused Inputs

Any unused UVIN_ inputs must be connected to V

, and

any unused OVIN_ inputs must be connected to GND.

UVOUT_

OVOUT_

Outputs

UVOUT_ and OVOUT_ outputs assert low when UVIN_

and OVIN_, respectively, drop below or exceed their

specified thresholds. The undervoltage/overvoltage out-

puts are open-drain with a (30µA) internal pullup to V

For many applications, no external pullup resistor is

required to interface with other logic devices. An external

pullup resistor to any voltage up to 5.5V overdrives the

internal pullup if interfacing to different logic supply volt-

ages. Internal circuitry prevents reverse current flow from

the external pullup voltage to V

(Figure 5). When

choosing the external pullup resistor, the resistance value

should be large enough to ensure that the output can sink

the necessary current during a logic-low condition and

small enough to be able to overdrive the internal pullup

current and meet output high specifications (V

Resistor values of 50kΩ to 200kΩ can generally be used.

RR R R

TOTAL

123=−−

VxR

TH TOTAL

TRIPLOW

23=−

VxR

TH TOTAL

TRIPHIGH

3 =

TRIPLOW

(%) =

⎛

⎝

⎜

⎞

⎠

⎟

100

((%)

(( ))

+IR xR

TRIPHIGH

22 1

100

LOAD

UVIN_

UVOUT_

MAX16063

GND

R3*

SUPPLY

*OPTIONAL. VALUES OF 10kΩ AND ABOVE ARE RECOMMENDED.

Figure 3. Overvoltage Shutdown Circuit (with External Pass

MOSFET)

LOAD

SCR

UVIN_

UVOUT_

MAX16063

GND

FUSE

SUPPLY

Figure 4. Overvoltage Shutdown Circuit (with SCR Fuse)

MAX16063

1% Accurate, Low-Voltage,

Quad Window Voltage Detector

______________________________________________________________________________________ 11

RESET

Output

RESET asserts low when the voltage on any of the

UVIN_ inputs falls below its respective threshold, the

voltage on any of the OVIN_ inputs goes above its

respective threshold, or MR is asserted. RESET

remains asserted for the reset timeout period after all

monitored UVIN_ inputs exceed their respective thresh-

olds, all OVIN_ inputs fall below their respective thresh-

olds, and MR is deasserted (see Figure 6). This

open-drain output has a 30µA internal pullup.

Reset Timeout Capacitor

The reset timeout period can be adjusted to accommo-

date a variety of microprocessor (µP) applications.

Adjust the reset timeout period (t

) by connecting a

capacitor (C

SRT

) between SRT and GND. Calculate the

reset timeout capacitor as follows:

Connect SRT to V

for a factory-programmed reset

timeout of 140ms (min).

Manual Reset Input (

)

Many µP-based products require manual reset capabil-

ity, allowing the operator, a test technician, or external

logic circuitry to initiate a reset. A logic-low on MR

asserts RESET low. RESET remains asserted while MR

is low, and during the reset timeout period (140ms min)

after MR returns high. The MR input has an internal

20kΩ pullup resistor to V

, so it can be left open if it is

not used. MR can be driven with TTL or CMOS-logic

levels, or with open-drain/collector outputs. Connect a

normally open momentary switch from MR to GND to

create a manual reset function; external debounce cir-

cuitry is not required. If MR is driven from long cables

or if the device is used in a noisy environment, connect-

ing a 0.1µF capacitor from MR to GND provides addi-

tional noise immunity.

SRT

TH SRT

SRT

()

⎛

⎝

⎜

⎞

⎠

⎟

MAX16063

GND

RESET

UVOUT_

= 3.3V

100kΩ

Figure 5. Interfacing to a Different Logic Supply Voltage

UVIN_

10%

90%

10%

90%

RESET

UVOUT_

TH_

+ V

TH_HYS

TH_

OVIN_

TH_

- V

TH_HYS

TH_

10%

90%

OVOUT_

Figure 6. Output Timing Diagram

Margin Output Disable (

MARGIN

)

MARGIN allows system-level testing while power sup-

plies are adjusted from their nominal voltages. Drive

MARGIN low to deassert all outputs (UVOUT_,

OVOUT_, and RESET) regardless of the voltage at any

monitored input. The state of each output does not

change while MARGIN = GND. While MARGIN is low,

the IC continues to monitor all voltages. When MARGIN

is deasserted, the outputs go to their monitored states

after a short propagation delay. The MARGIN input is

internally pulled up to V

. Leave unconnected or con-

nect to V

if unused.

Undervoltage Lockout (UVLO)

The MAX16063 features a V

undervoltage lockout

(UVLO) that preserves a reset status even if V

falls as

low as 1V. The undervoltage lockout circuitry monitors

the voltage at V

. If V

falls below the UVLO falling

threshold (typically 1.735V), RESET is asserted and all

detector outputs are asserted low. This eliminates an

incorrect RESET or detector output state as V

drops

below the normal V

operational voltage range of

1.98V to 5.5V.

During power-up as V

rises above 1V, RESET is assert-

ed and all detector outputs are asserted low until V

exceeds the UVLO threshold. As V

exceeds the UVLO

threshold, all inputs are monitored and the correct output

state appears at all the outputs. This also ensures that

RESET and all detector outputs are in the correct state

once V

reaches the normal V

operational range.

Power-Supply Bypassing

In noisy applications, bypass V

to ground with a

0.1µF capacitor as close to the device as possible. In

addition, the additional capacitor improves transient

immunity. For fast-rising V

transients, additional

capacitance may be required.

MAX16063

1% Accurate, Low-Voltage,

Quad Window Voltage Detector

12 ______________________________________________________________________________________

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

MAX16063TG+

Mfr. #:

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Manufacturer:

Maxim Integrated

Description:

Supervisory Circuits Quad Window Voltage Detector

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MAX16063TG+

MAX16063TG+

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