LTC3826
16
3826fc
APPLICATIONS INFORMATION
R
SENSE
Selection for Output Current
R
SENSE
is chosen based on the required output current.
The current comparator has a maximum threshold of
100mV/R
SENSE
and an input common mode range of
SGND to 10V. The current comparator threshold sets the
peak of the inductor current, yielding a maximum average
output current I
MAX
equal to the peak value less half the
peak-to-peak ripple current, ΔI
L
.
Allowing a margin for variations in the IC and external
component values yields:
R
mV
I
SENSE
MAX
=
80
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to the
internal compensation required to meet stability criterion
for buck regulators operating at greater than 50% duty
factor. A curve is provided in the Typical Performance Char-
acteristics section to estimate this reduction in peak output
current level depending upon the operating duty factor.
Operating Frequency and Synchronization
The choice of operating frequency, is a trade-off between
effi ciency and component size. Low frequency operation
improves effi ciency by reducing MOSFET switching losses,
both gate charge loss and transition loss. However, lower
frequency operation requires more inductance for a given
amount of ripple current.
The internal oscillator for each of the LTC3826’s controllers
runs at a nominal 390kHz frequency when the PLLLPF pin
is left fl oating and the PLLIN/MODE pin is a DC low or high.
Pulling the PLLLPF to INTV
CC
selects 530kHz operation;
pulling the PLLLPF to SGND selects 250kHz operation.
Alternatively, the LTC3826 will phase-lock to a clock
signal applied to the PLLIN/MODE pin with a frequency
between 140kHz and 650kHz (see Phase-Locked Loop
and Frequency Synchronization).
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is effi ciency. A higher
frequency generally results in lower effi ciency because
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current ΔI
L
decreases with higher
inductance or frequency and increases with higher V
IN
:
I
L
=
1
(f)(L
)
V
OUT
1–
V
OUT
V
IN
Accepting larger values of ΔI
L
allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ΔI
L
= 0.3(I
MAX
). The maximum
ΔI
L
occurs at the maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
10% of the current limit determined by R
SENSE
. Lower
inductor values (higher ΔI
L
) will cause this to occur at
lower load currents, which can cause a dip in effi ciency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High effi ciency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
xed inductor value, but it is very dependent on inductance
LTC3826
17
3826fc
APPLICATIONS INFORMATION
selected. As inductance increases, core losses go down.
Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode (Optional)
Selection
Two external power MOSFETs must be selected for each
controller in the LTC3826: one N-channel MOSFET for the
top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV
CC
voltage.
This voltage is typically 5V during start-up (see EXTV
CC
Pin
Connection). Consequently, logic-level threshold MOSFETs
must be used in most applications. The only exception
is if low input voltage is expected (V
IN
< 5V); then, sub-
logic level threshold MOSFETs (V
GS(TH)
< 3V) should be
used. Pay close attention to the BV
DSS
specifi cation for
the MOSFETs as well; most of the logic level MOSFETs are
limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R
DS(ON)
, Miller capacitance C
MILLER
, input
voltage and maximum output current. Miller capacitance,
C
MILLER
, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. C
MILLER
is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
at divided by the specifi ed change in V
DS
. This result is
then multiplied by the ratio of the application applied V
DS
to the Gate charge curve specifi ed V
DS
. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main SwitchDuty Cycle
V
V
OUT
IN
=
Synchronous SwitchDuty Cycle
VV
V
IN OUT
IN
=
The MOSFET power dissipations at maximum output
current are given by:
P
MAIN
=
V
OUT
V
IN
I
MAX
()
2
1+
()
R
DS(ON)
+
V
IN
()
2
I
MAX
2
R
DR
()
C
MILLER
()
1
V
INTVCC
–V
TH MIN
+
1
V
TH MIN
f
()
P
SYNC
=
V
IN
–V
OUT
V
IN
I
MAX
()
2
1+
()
R
DS(ON)
where δ is the temperature dependency of R
DS(ON)
and
R
DR
(approximately 2Ω) is the effective driver resistance
at the MOSFETs Miller threshold voltage. V
THMIN
is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I
2
R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V
IN
< 20V
the high current effi ciency generally improves with larger
MOSFETs, while for V
IN
> 20V the transition losses rapidly
increase to the point that the use of a higher R
DS(ON)
device
with lower C
MILLER
actually provides higher effi ciency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
LTC3826
18
3826fc
APPLICATIONS INFORMATION
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes D3 and D4 shown in Figure 14
conduct during the dead-time between the conduction of
the two power MOSFETs. This prevents the body diode of
the bottom MOSFET from turning on, storing charge during
the dead-time and requiring a reverse recovery period that
could cost as much as 3% in effi ciency at high V
IN
. A 1A
to 3A Schottky is generally a good compromise for both
regions of operation due to the relatively small average
current. Larger diodes result in additional transition losses
due to their larger junction capacitance.
C
IN
and C
OUT
Selection
The selection of C
IN
is simplifi ed by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can be
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
the highest (V
OUT
)(I
OUT
) product needs to be used in the
formula below to determine the maximum RMS capacitor
current requirement. Increasing the output current drawn
from the other controller will actually decrease the input
RMS ripple current from its maximum value. The out-of-
phase technique typically reduces the input capacitors RMS
ripple current by a factor of 30% to 70% when compared
to a single phase power supply solution.
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (V
OUT
)/(V
IN
). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
C
IN
RequiredI
RMS
I
MAX
V
IN
V
OUT
()
V
IN
–V
OUT
()
1/ 2
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT
/2. This simple worst-case condition is commonly
used for design because even signifi cant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3826, ceramic capacitors
can also be used for C
IN
. Always consult the manufacturer
if there is any question.
The benefi t of the LTC3826 2-phase operation can be cal-
culated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the same
time. The total RMS power lost is lower when both control-
lers are operating due to the reduced overlap of current
pulses required through the input capacitors ESR. This is
why the input capacitors requirement calculated above for
the worst-case controller is adequate for the dual controller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system. The overall benefi t of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the effi ciency testing.
The sources of the top MOSFETs should be placed within
1cm of each other and share a common C
IN
(s). Separating
the sources and C
IN
may produce undesirable voltage and
current resonances at V
IN
.
A small (0.1μF to 1μF) bypass capacitor between the chip V
IN
pin and ground, placed close to the LTC3826, is also sug-
gested. A 10Ω resistor placed between C
IN
(C1) and the V
IN
pin provides further isolation between the two channels.
The selection of C
OUT
is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfi ed, the capacitance is adequate for fi ltering. The
output ripple (ΔV
OUT
) is approximated by:
V
OUT
I
RIPPLE
ESR+
1
8fC
OUT

LTC3826EUH#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Ultra Low Iq, Dual, 2-Phase Synch Step Down Controller
Lifecycle:
New from this manufacturer.
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