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USB2.0 High-Speed (480Mbps) Signal Switch With Vbus Short Protection
2011-11-0004
PT0378-1 8/26/11
1
PI3USB42
Features
•
USB 2.0 compliant (high speed and full speed)
•
R
ON
is 4.0Ω typical @ V
DD
= 3.0V
•
Low bit-to-bit skew
•
Low Crosstalk: -41dB @ 240 MHz
•
Off Isolation: -37dB @ 240 MHz
•
Wide -3db bandwidth: 770MHz
•
Near-Zero propagation delay: 250ps
•
Support for 1.8V/2.5V/3.3V Logic on Control pins
•
Channel On Capacitance: 6.0pF
•
VDD Operating Range: 1.8V to 4.3V ±10%
•
Data pin I/O ESD: >8kV HBM protection per
JESD22-A114D specification
•
I/O pins have over-voltage protection and can
tolerate a short to Vbus
•
Packaging (Pb-free & Green): 10-pin UQFN (ZM10)
Applications
•
Route signals for USB 2.0
•
Cell phone, PDA, Digital camera and Notebook
•
LCD Monitor ,TV, Set-top box
•
Portable device
Pin Description
Pin No
Pin
Name
Description
1 D+ USB Data bus
2 D- USB Data bus
3 GND Ground
4 D-A Multiplexed Source Inputs
5 D+A Multiplexed Source Inputs
6 D-B Multiplexed Source Inputs
7 D+B Multiplexed Source Inputs
8 /OE Switch Enable
9 V
DD
Positive Power Supply
10 SEL Switch Select
Logic Function Table
/OE SEL Function
H X I/O’s = Hi-Z
L L D(+/-) to D(+/-)A
L H D(+/-) to D(+/-)B
Description
The PI3USB42 is a single differential channel 2:1
multiplexer/demultiplexer USB 2.0 Switch. Industry
leading advantages include a propagation delay of less
than 250ps, resulting from its low channel resistance and
I/O capacitance. The device multiplexes differential
outputs from a USB Host device to one of two
corresponding outputs. The switch is bidirectional and
offers little or no attenuation of the high-speed signals at
the outputs. It is designed for low bit-to-bit skew, high
channel-to-channel noise isolation and is compatible
with various standards, such as High Speed USB 2.0
(480 Mb/s).
The PI3USB42 offers overvoltage protection per the
USB2.0 specification. With the chip powered on or off,
all I/O pins can withstand a short to Vbus (5V +/-10%).
If VDD=0V, the I/Os can still have signals present, and
the signal will NOT leak through to VDD.
Functional Block Diagram
D-
SEL
D-A
D-B
D+
/OE
D+A
D+B
LOGIC
Pin Assignment