6.42
IDT70V9199/099L
High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
15
Depth and Width Expansion
The IDT70V9199/099 features dual chip enables (refer to Truth Table
I) in order to facilitate rapid and simple depth expansion with no require-
ments for external logic. Figure 4 illustrates how to control the varioius chip
enables in order to expand two devices in depth.
The IDT70V9199/099 can also be used in applications requiring
expanded width, as indicated in Figure 4. Since the banks are allocated
at the discretion of the user, the external controller can be set up to drive
the input signals for the various devices as required to allow for 18/16-bit
or wider applications.
4859 drw 18
IDT70V9199/099
CE
0
CE
1
V
DD
Control Inputs
CE
1
CE
0
Control Inputs
CE
0
CE
1
A
17
CE
1
CE
0
IDT70V9199/099
Control Inputs
Control Inputs
CNTRST
CLK
ADS
CNTEN
R/W
OE
V
DD
IDT70V9199/099
IDT70V9199/099
Figure 4. Depth and Width Expansion with IDT70V9199/099
Functional Description
The IDT70V9199/099 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH transition of the clock
signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to staff the
operation of the address counters for fast interleaved memory applications.
CE0 = VIL and CE1 = VIH for one clock cycle will power down the internal
circuitry to reduce static power consumption. Multiple chip enables allow
easier banking of multiple IDT70V9199/099's for depth expansion con-
figurations. When the Pipelined output mode is enabled, two cycles are
required with CE0 = VIH or CE1 = VIL to re-activate the outputs.
