6.42
IDT70V9199/099L
High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
2
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
10099 98 97
96 95 94
93 92 91 90
89 88 87 86 85
84 83 82 81 80 79 78 77 76
V
S
S
GND
FT/PIPE
R
OE
R
R/W
R
CNTRST
R
CE
1R
CE
0R
NC
NC
V
SS
A
12R
A
13R
A
11R
A
10R
A
9R
A
8R
A
7R
NC
NC
A
14R
NC
NC
4859 drw 02
NC
NC
FT/PIPE
L
OE
L
R/W
L
CNTRST
L
CE
1L
CE
0L
NC
NC
NC
V
DD
A
14L
A
13L
A
8L
A
7L
NC
NC
NC
A
12L
A
11L
A
10L
A
9L
I
/
O
6
R
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
I
/
O
2
R
I
/
O
0
R
I
/
O
0
L
I
/
O
1
L
V
S
S
I
/
O
2
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
3
L
I
/
O
1
R
I
/
O
7
R
I
/
O
8
L
I
/
O
8
R
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
C
N
T
E
N
R
C
L
K
R
A
D
S
R
A
D
S
L
C
L
K
L
C
N
T
E
N
L
A
0
L
A
2
L
A
3
L
A
5
L
A
6
L
A
1
L
A
4
L
N
C
N
C
V
D
D
V
S
S
V
D
D
V
S
S
V
S
S
N
C
N
C
N
C
70V9199PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
A
15R
A
16R
A
15L
NC
A
16L
.
04/02/03
Description:
The IDT70V9199/099 is a high-speed128K x9/x8 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times.
Pin Configuration
(1,2,3)
NOTES:
1. All V
DD pins must be connected to power supply.
2. All V
SS pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
With an input data register, the IDT70V9199/099 has been optimized
for applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE0 and CE1, permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 500mW of power.
