Data Sheet ADM8690/ADM8691/ADM8695
Rev. C | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
8
7
6
5
PFO
WDI
RESET
GND
PFI
ADM8690
TOP VIEW
(Not to Scale)
OUT
V
CC
V
BATT
00093-003
Figure 3. ADM8690 Pin Configuration,
8-Lead PDIP and 8-Lead SOIC_N
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
WDO
RESET
RESET
GND
PFO
WDI
BATT ON
LOW LINE
OSC IN
OSC SEL
PFI
ADM8691/
ADM8695
TOP VIEW
(Not to Scale)
V
BATT
V
OUT
V
CC
CE
IN
CE
OUT
00093-004
Figure 4. ADM8691/ADM8695 Pin Configuration, 16-Lead PDIP,
16-Lead SOIC_N, 16-Lead SOIC_W, and 16-Lead TSSOP
Table 4. Pin Function Descriptions
Pin No.
8-Lead 16-Lead Mnemonic Description
8 1 V
BATT
Backup Battery Input. V
BATT
or V
CC
is internally switched to V
OUT
, depending on which is at the
highest potential.
1 2 V
OUT
Output Voltage. V
CC
or V
BATT
is internally switched to V
OUT
, depending on which is at the highest
potential. V
OUT
can supply up to 100 mA to power CMOS RAM. Connect V
OUT
to V
CC
if V
OUT
and V
BATT
are not used.
2 3 V
CC
Power Supply Input. 5 V nominal. V
CC
or V
BATT
is internally switched to V
OUT
, depending on which is
at the highest potential.
3 4 GND Ground. This is the 0 V ground reference for all signals.
N/A 5 BATT ON
Logic Output. BATT ON goes high when V
OUT
is internally switched to the V
BATT
input. It goes low
when V
OUT
is internally switched to V
CC
. The output typically sinks 35 mA and can directly drive the
base of an external PNP transistor to increase the output current above the 100 mA rating of V
OUT
.
N/A 6
LOW LINE
Logic Output. LOW LINE goes low when V
CC
falls below the reset threshold. It returns high as
soon as V
CC
rises above the reset threshold.
N/A 7 OSC IN
Oscillator Logic Input. When OSC SEL is low, OSC IN can be driven by an external clock signal, or
an external capacitor can be connected between OSC IN and GND. This sets both the reset active
pulse timing and the watchdog timeout period (see Table 5 and Figure 17 through Figure 20).
When OSC SEL is high or floating, the internal oscillator is enabled and the reset active time is
fixed at 50 ms typical (ADM8691) or 200 ms typical (ADM8695). In this mode, the OSC IN pin
selects either the fast (100 ms) or slow (1.6 sec) watchdog timeout period. In both modes, the
timeout period immediately after a reset is 1.6 sec typical.
N/A 8 OSC SEL
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal
oscillator sets the reset active time and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled (see Table 5). OSC SEL has a 5 µA internal pull-up.
4 9 PFI
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than
1.3 V, PFO
goes low. Connect PFI to GND or V
OUT
when not used.
5 10
PFO
Power-Fail Output. PFO is the output of the power-fail comparator. It goes low when PFI is less
than 1.3 V. The comparator is turned off and PFO goes low when V
CC
is below V
BATT
.
6 11 WDI
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than
the watchdog timeout period, RESET
pulses low and WDO goes low. The timer is reset with each
transition on the WDI line. The watchdog timer can be disabled if WDI is left floating or is driven
to midsupply.
N/A 12
CE
OUT
Logic Output. CE
OUT
is a gated version of the CE
IN
signal. CE
OUT
tracks CE
IN
when V
CC
is above the reset
threshold. If V
CC
is below the reset threshold, CE
OUT
is forced high. See and . Figure 21 Figure 22
N/A 13
CE
IN
Logic Input. Input to the CE gating circuit. When not in use, connect this pin to GND or V
OUT
.
N/A 14
WDO
Logic Output. The watchdog output, WDO, goes low if WDI remains either high or low for longer
than the watchdog timeout period. WDO
is set high by the next transition at WDI. If WDI is
unconnected or at midsupply, the watchdog timer is disabled and WDO remains high. WDO also
goes high when LOW LINE goes low.
