1. General description
The 74HC4020; 74HCT4020 are high-speed Si-gate CMOS devices and are pin
compatible with the HEF4020B series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC4020; 74HCT4020 are 14-stage binary ripple counters with a clock input (CP
),
an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0, Q3
to Q13). The counter advances on the HIGH-to-LOW transition of CP
.
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
state of CP
.
Each counter stage is a static toggle flip-flop.
2. Features and benefits
Multiple package options
Complies with JEDEC standard no. 7A
Specified from 40 Cto+85C and from 40 Cto+125C
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
4. Ordering information
74HC4020; 74HCT4020
14-stage binary ripple counter
Rev. 5 — 6 August 2012 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC4020N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT4020N
74HC4020D 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74HCT4020D
74HC4020DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body
width 5.3 mm
SOT338-1
74HCT4020DB
