MAX395
Serially Controlled, Low-Voltage,
8-Channel SPST Switch
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_______________Detailed Description
Basic Operation
The MAX395’s interface can be thought of as an 8-bit
shift register controlled by CS (Figure 2). While CS is
low, input data appearing at DIN is clocked into the
shift register synchronously with SCLK’s rising edge.
The data is an 8-bit word, each bit controlling one of
eight switches in the MAX395 (Table 1). DOUT is the
shift register’s output, with data appearing synchro-
nously with SCLK’s falling edge. Data at DOUT is sim-
ply the input data delayed by eight clock cycles.
When shifting the input data, D7 is the first bit in and
out of the shift register. While shifting data, the switches
remain in their previous configuration. When the eight
bits of data have been shifted in, CS is driven high. This
updates the new switch configuration and inhibits fur-
ther data from entering the shift register. Transitions at
DIN and SCLK have no effect when CS is high, and
DOUT holds the first input bit (D7) at its output.
More or less than eight clock cycles can be entered
during the CS low period. When this happens, the shift
register will contain only the last eight serial data bits,
regardless of when they were entered. On the rising
edge of CS
, all the switches will be set to the corre-
sponding states.
The MAX395’s three-wire serial interface is compatible
with SPI™, QSPI™, and Microwire™ standards. If inter-
facing with a Motorola processor serial interface, set
CPOL = 0. The MAX395 is considered a slave device
(Figures 2 and 3). Upon power-up, the shift register
contains all zeros, and all switches are off.
The latch that drives the analog switch is updated on
the rising edge of CS, regardless of SCLK’s state. This
meets all the SPI and QSPI requirements.
Daisy Chaining
For a simple interface using several MAX395s, “daisy
chain” the shift registers as shown in Figure 5. The CS
pins of all devices are connected together, and a
stream of data is shifted through the MAX395s in series.
When CS is brought high, all switches are updated
simultaneously. Additional shift registers may be includ-
ed anywhere in series with the MAX395 data chain.
• • •
• • •
• • •
• • •
• • •
SCLK
DIN
DOUT
COM OUT
CS
t
DO
t
DH
t
DS
t
CSH0
t
CSS
t
CH
t
CL
t
CSH1
t
CSH2
t
CLL
t
OFF
Figure 1. Timing Diagram
