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LTC3526EDC-2#TRMPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LTC3526-2/LTC3526B-2
13
35262b2fc
typicAl ApplicAtions
2-Cell to 5V
SW
V
IN
3.24M
3.3µH*
1.02M
*TAIYO-YUDEN NP03SB3R3M
1µF
10µF
22pF
35262b2 TA06a
LTC3526-2
SHDN
V
OUT
FB
V
IN
2V TO 3.2V
V
OUT
5V
150mA
OFF ON
GND
Li-Ion to 5V
SW
V
IN
3.24M
3.3µH*
1.02M
*TAIYO-YUDEN NP03SB3R3M
1µF
10µF
22pF
35262b2 TA08a
LTC3526-2
SHDN
V
OUT
FB
V
IN
2.7V TO 4.3V
V
OUT
5V
200mA
OFF ON
GND
LOAD CURRENT (mA)
0.01
40
EFFICIENCY (%)
50
60
70
80
0.1 1 10 100 1000
35262b2 TA06b
30
20
10
0
90
100
V
IN
= 3.0V
V
IN
= 2.4V
V
IN
= 1.8V
V
OUT
= 5V
LOAD CURRENT (mA)
0.01
40
EFFICIENCY (%)
50
60
70
80
0.1 1 10 100 1000
35262b2 TA08b
30
20
10
0
90
100
V
IN
= 4.2V
V
IN
= 3.6V
V
IN
= 3.0V
V
OUT
= 5V
LTC3526-2/LTC3526B-2
14
35262b2fc
pAckAge Description
2.00 p0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
0.56 p 0.05
(2 SIDES)
0.75 p0.05
R = 0.125
TYP
R = 0.05
TYP
1.37 p0.05
(2 SIDES)
1
3
64
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DC6) DFN REV B 1309
0.25 p 0.05
0.50 BSC
0.25 p 0.05
1.42 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.61 p0.05
(2 SIDES)
1.15 p0.05
0.70 p0.05
2.55 p0.05
PACKAGE
OUTLINE
0.50 BSC
PIN 1 NOTCH
R = 0.20 OR
0.25 s 45o
CHAMFER
DC Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703 Rev B)
LTC3526-2/LTC3526B-2
15
35262b2fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision history
REV DATE DESCRIPTION PAGE NUMBER
C 9/10
Updated θ
JA
on Pin Configuration
Updated Note 6
Updated Shutdown section
Updated Related Parts
2
3
8
16
(Revision history begins at Rev C)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

LTC3526EDC-2#TRMPBF

Mfr. #:
Buy LTC3526EDC-2#TRMPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 500mA, 2MHz Synch Step -Up in DFN
Lifecycle:
New from this manufacturer.
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