ZL30112LDG1 Datasheet ZL30112LDG1 | P13-P15

ZL30112 Data Sheet

Zarlink Semiconductor Inc.

6.3 Jitter Transfer

Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter

at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured

with various filters depending on the applicable standards. For the ZL30112, the internal low pass loop filter

determines the jitter attenuation.

Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for

large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter

signals (for example 75% of the specified maximum tolerable input jitter).

6.4 Freerun Accuracy

Frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an

external reference, but is operating in a free running mode. For the ZL30112, the Freerun accuracy is equal to the

master clock (OSCi) accuracy.

6.5 Capture Range

Also referred to as pull-in range. This is the input frequency range over which the PLL must be able to pull into

synchronization. The ZL30112 capture range is equal to

±130 ppm minus the accuracy of the master clock (OSCi).

For example, a +32 ppm master clock results in a capture range of +162 ppm on one side and -98 ppm on the other

side of frequency range.

6.6 Lock Range

This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock

range is equal to the capture range for the ZL30112.

6.7 Time Interval Error (TIE)

TIE is the time delay between a given timing signal and an ideal timing signal.

6.8 Maximum Time Interval Error (MTIE)

MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a

particular observation period.

6.9 Phase Continuity

Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a

particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.

Phase continuity applies to the output of the PLL after a signal disturbance due to a reference switch or a mode

change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to

a steady state.

ZL30112 Data Sheet

Zarlink Semiconductor Inc.

6.10 Phase Lock Time

This is the time it takes the PLL to phase lock to the input signal. Phase lock occurs when the input signal and

output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter).

Lock time is affected by many factors which include:

• initial input to output phase difference

• initial input to output frequency difference

• PLL loop filter bandwidth

• in-lock phase distance

The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output

to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and

frequency.

Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.

For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock

time. See Section 8.2, “Performance Characteristics“ for Maximum Phase Lock Time.

7.0 Applications

This section contains ZL30112 application specific details for power supply decoupling, clock and crystal operation,

reset operation, and control operation.

7.1 Power Supply Decoupling

Jitter levels on the ZL30112 output clocks may increase if the device is exposed to excessive noise on its power

pins. For optimal jitter performance, the ZL30112 device should be isolated from noise on power planes connected

to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note

ZLAN-178.

7.2 Master Clock

The ZL30112 can use either a clock or crystal as the master timing source. Zarlink Application Note ZLAN-68 lists a

number of applicable oscillators and crystals that can be used with the ZL30112.

7.2.1 Clock Oscillator

When selecting a Clock Oscillator, numerous parameters must be considered. These includes absolute frequency,

frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.

1 Frequency 20 MHz

2 Tolerance As required

3Rise & Fall Time <10ns

4 Duty Cycle 40% to 60%

Table 1 - Typical Clock Oscillator Specification

ZL30112 Data Sheet

Zarlink Semiconductor Inc.

The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30112 and the OSCo

output should be left open as shown in Figure 6.

Figure 6 - Clock Oscillator Circuit

7.2.2 Crystal Oscillator

Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a crystal, resistor and

capacitors is shown in Figure 7.

The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance.

Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load capacitance

contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances and stray

capacitances have a major effect on the accuracy of the oscillator frequency.

The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler

oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal

specification is as follows.

1 Frequency 20 MHz

2 Tolerance As required

3 Oscillation Mode Fundamental

4 Resonance Mode Parallel

5 Load Capacitance As required

6 Maximum Series Resistance 50 Ω

Table 2 - Typical Crystal Oscillator Specification

+3.3 V

20 MHz OUT

GND 0.1 µF

+3.3 V

OSCo

ZL30112

OSCi

No Connection

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