ALD1704A/ALD1704B Advanced Linear Devices 4 of 9
ALD1704/ALD1704G
TYPICAL PERFORMANCE CHARACTERISTICS
Design & Operating Notes:
1. The ALD1704A/ALD1704B/ALD1704/ALD1704G CMOS operational
amplifier uses a 3 gain stage architecture and an improved frequency
compensation scheme to achieve large voltage gain, high output
driving capability, and better frequency stability. The ALD1704A/
ALD1704B/ALD1704/ALD1704G is internally compensated for unity
gain stability using a novel scheme that produces a clean single pole
roll off in the gain characteristics while providing for more than 70
degrees of phase margin at the unity gain frequency. A unity gain buffer
using the ALD1704A/ALD1704B/ALD1704/ALD1704G will typically
drive 400pF of external load capacitance without stability problems. In
the inverting unity gain configuration, it can drive up to 800pF of load
capacitance. Compared to other CMOS operational amplifiers, the
ALD1704A/ALD1704B/ALD1704/ALD1704G has shown itself to be
more resistant to parasitic oscillations.
2. The ALD1704A/ALD1704B/ALD1704/ALD1704G has complementary
p-channel and n-channel input differential stages connected in parallel
to accomplish rail to rail input common mode voltage range. This
means that with the ranges of common mode input voltage close to the
power supplies, one of the two differential stages is switched off
internally. To maintain compatibility with other operational amplifiers,
this switching point has been selected to be about 1.5V above the
negative supply voltage. Since offset voltage trimming on the ALD1704A/
ALD1704B/ALD1704/ALD1704G is made when the input voltage is
symmetrical to the supply voltages, this internal switching does not
affect a large variety of applications such as an inverting amplifier or
non-inverting amplifier with a gain larger than 2 (10V operation), where
the common mode voltage does not make excursions below this
switching point.
3. The input bias and offset currents are essentially input protection diode
reverse bias leakage currents, and are typically less than 1pA at room
temperature. This low input bias current assures that the analog signal
from the source will not be distorted by input bias currents. For
applications where source impedance is very high, it may be necessary
to limit noise and hum pickup through proper shielding.
4. The output stage consists of symmetrical class AB complementary
output drivers, capable of driving a low resistance load with up to 10mA
source current and 10mA sink current. The output voltage swing is
limited by the drain to source on-resistance of the output transistors as
determined by the bias circuitry, and the value of the load resistor.
When connected in the voltage follower configuration, the oscillation
resistant feature, combined with the rail-to-rail input and output feature,
makes the ALD1704A/ALD1704B/ALD1704/ALD1704G an effective
analog signal buffer for medium to high source impedance sensors,
transducers, and other circuit networks.
5. The ALD1704A/ALD1704B/ALD1704/ALD1704G operational ampli-
fier has been designed to provide full static discharge protection.
Internally, the design has been carefully implemented to minimize latch
up. However, care must be exercised when handling the device to
avoid strong static fields that may degrade a diode junction, causing
increased input leakage currents. In using the operational amplifier, the
user is advised to power up the circuit before, or simultaneously with,
any input voltages applied and to limit input voltages to not exceed 0.3V
of the power supply voltage levels.
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
1000
100
10
0.1
1.0
INPUT BIAS CURRENT (pA)
100-25 0 75 1255025-50
V
S
= ±5.0V
10000
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
COMMON MODE INPUT
VOLTAGE RANGE (V)
±7
±6
±5
±4
±3
±2
±2
±3
±4
±5
±6 ±7
T
A
= 25°C
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
5
4
3
2
1
0
SUPPLY CURRENT (mA)
0 ±1 ±2 ±3 ±4 ±5 ±6
+125°C
+80°C
+25°C
T
A
= -55°C
-25°C
INPUTS GROUNDED
OUTPUT UNLOADED
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGE AND TEMPERATURE
SUPPLY VOLTAGE (V)
1000
100
10
1
OPEN LOOP VOLTAGE
GAIN (V/mV)
0 ±2 ±4 ±6
R
L
= 10KΩ
R
L
= 5KΩ
} -55°C
} +25°C
} +125°C
±8
