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5 Manufacturing Information
5.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classifies its plastic encapsulated devices for moisture sensitivity according to the latest
version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation.
We test all of our products to the maximum conditions set forth in the standard, and guarantee proper
operation of our devices when handled according to the limitations and information in that standard as well as to any
limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled
according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
5.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard JESD-625.
5.3 Soldering Profile
Provided in the table below is the Classification Temperature (T
C
) of this product and the maximum dwell time the
body temperature of this device may be (T
C
- 5)ºC or greater. The classification temperature sets the Maximum Body
Temperature allowed for this device during lead-free reflow processes. For through-hole devices, and any other
processes, the guidelines of J-STD-020 must be observed.
5.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. Board washing to reduce or
remove flux residue following the solder reflow process is acceptable provided proper precautions are taken to
prevent damage to the device. These precautions include but are not limited to: using a low pressure wash and
providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the washing
process. Due to the variability of the wash parameters used to clean the board, determination of the bake temperature
and duration necessary to remove the moisture trapped within the package is the responsibility of the user
(assembler). Cleaning or drying methods that employ ultrasonic energy may damage the device and should not be
used. Additionally, the device must not be exposed to flux or solvents that are Chlorine- or Fluorine-based.
Device Moisture Sensitivity Level (MSL) Classification
IXD_609 All Versions except IXD_609YI MSL 1
IXD_609YI MSL 3
Device
Classification Temperature (T
C
) Dwell Time (t
p
)
Maximum Cycles
IXD_609CI 245°C for 30 seconds 30 seconds 1
IXD_609YI 245°C for 30 seconds 30 seconds 3
IXD_609PI 250°C for 30 seconds 30 seconds 3
IXD_609SI / IXD_609SIA / IXD_609D2 260°C for 30 seconds 30 seconds 3
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IXD_609
R08 www.ixysic.com 11
5.5 Mechanical Dimensions
5.5.1 SIA (8-Pin SOIC)
5.5.2 SI (8-Pin Power SOIC with Exposed Metal Back)
Note:
The exposed metal pad on the back of the SI package should be connected to GND. It is not suitable for
carrying current.
NOTES:
1. Complies with JEDEC Standard MS-012.
2. All dimensions are in millimeters.
3. Dimensions do not include mold flash or burrs
PCB Land Pattern
Pin 1
Pin 8
3.90 ± 0.10
6.00 ± 0.20
0.42 ± 0.09
4.90 ± 0.10
1.27 REF
1.25 min
0.175 ± 0.075
0.40 min
1.27 max
1.27
5.60
1.75
0.65
1.75 max
Recommended PCB Land Pattern
Dimensions
mm
(inches)
1.346 ± 0.076
(0.053 ± 0.003)
0.051 MIN - 0.254 MAX
(0.002 MIN - 0.010 MAX)
4.928 ± 0.254
(0.194 ± 0.010)
Pin 1
0.406 ± 0.076
(0.016 ± 0.003)
5.994 ± 0.254
(0.236 ± 0.010)
3.937 ± 0.254
(0.155 ± 0.010)
1.270 REF
(0.050)
0.762 ± 0.254
(0.030 ± 0.010)
2.540 ± 0.254
(0.100 ± 0.010)
3.556 ± 0.254
(0.140 ±0.010)
1.27
(0.050)
5.40
(0.209)
1.55
(0.061)
0.60
(0.024)
2.75
(0.108)
3.80
(0.150)
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5.5.3 Tape & Reel Information for SI and SIA Packages
5.5.4 YI (5-Pin TO-263)
Dimensions
mm
(inches)
NOTE:
Tape dimensions not shown comply with JEDEC Standard EIA-481-2
Embossment
Embossed Carrier
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
330.2 DIA.
(13.00 DIA.)
K
0
= 2.10
(0.083)
W=12.00
(0.472)
B
0
=5.30
(0.209)
User Direction of Feed
A
0
=6.50
(0.256)
P=8.00
(0.315)
H
b1
c1
b
c
SECTION: C-C
PLATING
(Note 3)
BASE METAL
E
(Note 2)
D1
D
(Note 2)
L1
e ~4x
CC
E3
D2
*
b ~5x
E1
NOTES:
1. Reference JEDEC TO-263 Type “BA”.
2. Dimension does not include mold flash; mold flash
shall not exceed 0.127mm (0.005 inch) per side.
3. Minimum plating: 1000 microinches.
4. Controlling dimension: millimeters.
MIN MINMAX MAX
MM INCH
SYMBOL
1.702 BSC 0.067 BSC
0.254 BSC 0.010 BSC
0.460 TYP 0.018 TYP
0.506 TYP
0.02 TYP
4.8264.064 0.160 0.190
0.2540.000 0.000 0.010
0.9910.508 0.020 0.039
0.8890.508 0.020 0.035
0.7370.381 0.015 0.029
0.5840.381 0.015 0.023
1.6511.143 0.045 0.065
9.6528.382 0.330 0.380
7.7006.858 0.270 0.303
10.6689.652 0.380 0.420
8.0006.223 0.245 0.315
15.87514.605 0.575 0.625
2.7941.778 0.070 0.110
1.6761.000 0.039 0.066
8º--8º
A
θ
A1
b
b1
c
c1
c2
D
D1
E
E1
e
H
L
L1
L3
R
R1
6.8695.092 0.200 0.270E3
1.5621.358 0.053 0.062D2
A1
L
L3
θ
R
R
A
c2
A1
L
L3
θ
R1
R1
JEDEC TO-263
Optional Tip Lead Form
Recommended PCB Pattern
10.75
(0.423)
2.20
(0.087)
8.40
(0.331)
8.05
(0.317)
10.50
(0.413)
1.05
(0.041)
3.80
(0.150)
1.702
(0.067)
Dimensions
mm
(inches)
Pin 1
Indicator
Circular feature will be
present on devices
with the
Optional Tip Lead Form.
*

IXDN609SITR

Mfr. #:
Manufacturer:
IXYS Integrated Circuits
Description:
Gate Drivers 9-Ampere Low-Side Ultrafast MOSFET
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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