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74AVC16334ADGG,118

P1-P3P4-P6P7-P9P10-P11
Philips Semiconductors Product specification
74AVC16334A
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs (3-State)
2000 Aug 03
6
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
≤ 2.0 ns; C
L
= 30 pF
LIMITS
SYMBOL PARAMETER WAVEFORM
V
CC
= 3.3 ± 0.3 V V
CC
= 2.5 ± 0.2 V V
CC
= 1.8 ± 0.15 V
V
CC
=
1.5 ± 0.1 V
V
CC
=
1.2 V
UNIT
MIN TYP
1
MAX MIN TYP
1
MAX MIN TYP
1
MAX MIN MAX TYP
Propagation
delay
An to Yn
1 0.7 1.5 2.6 0.8 1.7 3.0 1.0 2.5 4.4 1.7 5.3 5.0
t
PHL
/t
PLH
Propagation
delay
LE
to Yn
2 0.7 1.6 3.2 1.0 2.0 3.3 1.2 2.7 4.8 1.7 6.0 5.3
ns
Propagation
delay
CP to Yn
3 0.7 1.6 2.8 0.8 1.7 3.0 1.0 2.3 3.9 1.4 4.6 4.1
t
PZH
/t
PZL
3-State output
enable time
OE
to Yn
6 0.7 1.7 3.4 1.0 2.2 3.8 1.5 3.1 5.3 2.0 6.7 6.0 ns
t
PHZ
/t
PLZ
3-State output
disable time
OE to Yn
6 1.0 2.1 3.7 0.9 2.0 3.9 1.5 3.7 6.5 1.7 7.1 6.1 ns
t
CP pulse width
HIGH or LOW
3 1.0 – – 1.2 – – 2.0 – – – – –
ns
t
W
LE pulse width
LOW
2 1.0 – – 1.2 – – 2.0 – – – – –
ns
t
S
Set-up time
An to CP
5 0.2 –0.1 – 0.1 –0.1 – 0.1 –0.1 – 0.1 – 0.0
ns
t
SU
Set-up time
An to LE
4 0.4 0.1 – 0.5 0.1 – 0.8 0.3 – 1.2 – 1.0
ns
t
Hold time
An to CP
5 0.6 0.2 – 0.6 0.2 – 0.6 0.2 – 0.6 – 0.1
ns
t
h
Hold time
An to LE
4 0.4 0.1 – 0.4 0.1 – 0.3 0.1 – 0.3 – –0.4
ns
f
max
Maximum clock
pulse frequency
3 500 – – 400 – – 250 – – – – – MHz
NOTE:
1. All typical values are measured at T
amb
= 25°C and at V
CC
= 1.8 V, 2.5 V, 3.3 V.
Philips Semiconductors Product specification
74AVC16334A
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs (3-State)
2000 Aug 03
7
AC WAVEFORMS FOR V
CC
= 3.0 V TO 3.6 V RANGE
V
M
= 0.5 V
CC
V
X
= V
OL
+ 0.300 V
V
Y
= V
OH
– 0.300 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
I
= V
CC
AC WAVEFORMS FOR V
CC
= 2.3 V TO 2.7 V AND
V
CC
< 2.3 V RANGE
V
M
= 0.5 V
CC
V
X
= V
OL
+ 0.15 V
V
Y
= V
OH
– 0.15 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
I
= V
CC
A
n
INPUT
t
PHL
t
PLH
V
OL
V
I
GND
V
OH
Y
n
OUTPUT
SH00132
V
M
V
M
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 1. Input (An) to output (Yn) propagation delay
LE INPUT
Yn OUTPUT
V
I
GND
V
OH
V
OL
t
PHL
t
PLH
t
W
V
M
V
M
V
M
SH00165
NOTE: V
M
= 0.5 V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Yn) propagation delays.
CP INPUT
Yn OUTPUT
V
I
GND
V
OH
V
OL
t
PHL
t
PLH
t
W
1/f
MAX
SH00135
V
M
V
M
V
M
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 3. The clock (CP) to Yn propagation delays, the
clock pulse width and the maximum clock frequency.
An
INPUT
LE
INPUT
t
SU
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
t
SU
th
V
I
GND
V
I
GND
V
M
V
M
SH00166
V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 4. Data set-up and hold times for the An input to the
LE
input
V
I
GND
An INPUT
V
I
GND
V
OH
Yn OUTPUT
V
OL
CP INPUT
t
su
t
h
t
su
t
h
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SH00136
V
M
V
M
V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 5. Data set-up and hold times for the An input to the
clock CP input
t
PLZ
t
PZL
V
I
nOE INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SH00137
NOTE: V
M
= 0.5V
CC
at V
CC
= 2.3 to 2.7 V
Waveform 6. 3-State enable and disable times
Philips Semiconductors Product specification
74AVC16334A
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs (3-State)
2000 Aug 03
8
TEST CIRCUIT
SWITCH POSITION
PULSE
GENERATOR
R
T
V
I
D.U.T.
V
O
C
L
V
CC
R
L
Test Circuit for switching times
Open
GND
S
1
DEFINITIONS
V
CC
V
I
< 2.3 V V
CC
TEST S
1
t
PLH/
t
PHL
Open
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
2 V
CC
t
PLZ/
t
PZL
V
CC
2.3–2.7 V
t
PHZ/
t
PZH
GND
R
L
2 * V
CC
SV01018
R
L
1000 Ω
500 Ω
V
CC
3.0 V 500 Ω
Waveform 7. Load circuitry for switching times
GRAPHS
SH00204
0
0.5
1
1.5
2
2.5
3
3.5
0 50 100 150 200 250
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
= 3.3 V
V
OL
V
CC
= 2.5 V
V
CC
V
CC
= 1.8 V
I
OL
Figure 1. Output voltage (V
OL
) vs. output current (I
OL
)
SH00205
–250 –200 –150 –100
–50
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
= 3.3 V
= 2.5 V = 1.8 V
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
V
OH
V
CC
I
OH
V
CC
V
CC
Figure 2. Output voltage (V
OH
) vs. output current (I
OH
)
A Dynamic Controlled Output (DCO) circuit is designed in. During
the transition, it initially lowers the output impedance to effectively
drive the load and, subsequently, raises the impedance to reduce
noise. Figures 1 and 2 show V
OL
vs. I
OL
and V
OH
vs. I
OH
curves to
illustrate the output impedance and drive capability of the circuit. At
the beginning of the signal transition, the DCO circuit provides a
maximum dynamic drive that is equivalent to a high drive standard
output device.
P1-P3P4-P6P7-P9P10-P11

74AVC16334ADGG,118

Mfr. #:
Buy 74AVC16334ADGG,118
Manufacturer:
Nexperia
Description:
Latches IC UNIV BUS DVR 16BIT
Lifecycle:
New from this manufacturer.
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