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96D4I-8G2400R-ATL

P1-P3P4-P6P7-P9P10-P11
A
A
T
T
P
P
A
A
4
4
B
B
0
0
8
8
Q
Q
G
G
8
8
B
B
N
N
R
R
C
C
S
S
W
W
Y
Y
o
o
u
u
r
r
U
U
l
l
t
t
i
i
m
m
a
a
t
t
e
e
M
M
e
e
m
m
o
o
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r
y
y
S
S
o
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!
!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 7 of 11
ABSOLUTE MAXIMUM DC RATINGS
Item Symbol Rating Units Notes
Voltage on V
DD
pin relative to V
SS
V
DD
-0.4V ~ 1.5V V 1,3
Voltage on V
DDQ
pin relative to V
SS
V
DDQ
-0.4V ~ 1.5V V 1,3
Voltage on V
PP
pin relative to V
SS
V
PP
-0.4V ~ 3.0V V 4
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.4V ~ 1.975V V 1
Storage Temperature T
STG
-55 to +100
o
C 1,2
Operating Temperature
T
CASE
-40 to +95
o
C 1,2,5
T
A
-40 to +85
o
C
1,6,7
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV;
VREFCA may be equal to or less than 300 mV
4. VPP must be equal or greater than VDD/VDDQ at all times.
5. At 85 - 95 oC operation temperature range, doubling refresh commands in frequency to a 32ms period ( Refresh interval =3.9 μs ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
6. Both temperature specifications must be satisfied.
7. Operating ambient temperature surrounding the package
AC & DC OPERATING CONDITIONS
Recommended operating conditions
Item Symbol Min. Typical Max. Units
Supply Voltage
1
,
2
,
3
V
DD
1.14 1.2 1.26 V
Supply Voltage for Output
1
,
2
,
3
V
DDQ
1.14 1.2 1.26 V
DRAM Activating Power Supply
3
V
PP
2.375 2.5 2.75 V
Input reference voltage command/
address bus
V
REFCA(DC) 0.49 * V
DD
0.50 * V
DD
0.51 * V
DD
V
Termination reference voltage (DC) –
command/address bus
4
V
TT
0.49 * V
DD
-
20mA
0.50 * V
DD
0.51 * V
DD
+
20mA
V
Input High Voltage (DC) V
IH
(DC) V
REF
+ 0.075 - V
DD
V
Input High Voltage (AC) V
IH
(AC) V
REF
+ 0.1 - - V
Input Low Voltage (DC) V
IL
(DC) V
SS
- V
REF
- 0.075 V
Input Low Voltage (AC) V
IL
(AC) - - V
REF
- 0.1 V
Note:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. DC bandwidth is limited to 20MHz.
4. VTT termination voltages in excess of specification limit will adversely affect command and address signals' voltage margins, and reduce timing margins.
RELIABILITY
MTBF @25
o
C
(Hours)
1
FIT @ 25
o
C
2
MTBF @40
o
C (Hours)
1
FIT @ 40
o
C
2
7,383,000 135 4,454,000 225
Note:
1. The Mean Time between Failures (MTBF) is calculated using a prediction methodology, Bellcore Prediction, which based on reliability data of the individual
components in the module. It assumes nominal voltage, with all other parameters within specified range.
2. Failures per Billion Device-Hours
A
A
T
T
P
P
A
A
4
4
B
B
0
0
8
8
Q
Q
G
G
8
8
B
B
N
N
R
R
C
C
S
S
W
W
Y
Y
o
o
u
u
r
r
U
U
l
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a
a
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M
e
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y
y
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S
o
o
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u
u
t
t
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o
o
n
n
!
!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 8 of 11
IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (PART1 OF 2)
Values are for the DDR4 SDRAM only and are computed from values specified in the vendor’s component data sheet)
Symbol Proposed Conditions Value Units
IDD0
Operating One Bank Active-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High
between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling; Data IO: VDDQ; DM_n:
stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode
Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
610 mA
IPP0
Operating One Bank Active-Precharge IPP Current
Same condition with IDD0
36
mA
IDD1
Operating One Bank Active-Read-Precharge Current (AL=0)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n:
High between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially toggling;
DM_n: sta-ble at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode
Registers2; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
830
mA
IDD2N
Precharge Standby Current (AL=0)
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1; Bank
Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer to
Component Datasheet for detail pattern
510
mA
IDD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VSSQ; DM_n: stable at 1; Bank
Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: toggling according ; Pattern Details:
Refer to Component Datasheet for detail pattern
530
mA
IDD2P
Precharge Power-Down Current
CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0
320
mA
IDD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0
500
mA
IDD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at 1;Bank
Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details:Refer to
Component Datasheet for detail pattern
600
mA
IPP3N
Active Standby IPP Current
Same condition with IDD3N
27
mA
IDD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: sRefer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: stable at 1;
Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0
360
mA
IDD4R
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 82; AL: 0; CS_n: High between RD;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different
data between one burst and the next one according ; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling
through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: Refer
to Component Datasheet for detail pattern
1,330
mA
A
A
T
T
P
P
A
A
4
4
B
B
0
0
8
8
Q
Q
G
G
8
8
B
B
N
N
R
R
C
C
S
S
E
E
Y
Y
o
o
u
u
r
r
U
U
l
l
t
t
i
i
m
m
a
a
t
t
e
e
M
M
e
e
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r
y
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S
S
o
o
l
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u
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t
t
i
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o
o
n
n
!
!
Page 9 of 11
IDD SPECIFICATION PARAMETER & POWER CONSUMPTION (PART2 OF 2)
Values are for the DDR4 SDRAM only and are computed from values specified in the vendor’s component data sheet)
Symbol Proposed Conditions Value Units
IDD4W
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High between WR;
Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different
data between one burst and the next one ; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through banks:
0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at HIGH; Pattern Details: Refer to
Component Datasheet for detail pattern
1,190
mA
IDD5B
Burst Refresh Current (1X REF)
CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n: High
between REF; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling ; Data IO: VDDQ; DM_n: stable at
1; Bank Activity: REF command every nRFC ; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern
Details: Refer to Component Datasheet for detail pattern
2,070
mA
IPP5B
Burst Refresh Write IPP Current (1X REF)
Same condition with IDD5B
162
mA
IDD6N
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL:
Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address,
Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT
Signal: MID-LEVEL
220
mA
IDD6E
Self-Refresh Current: Extended Temperature Range)
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock: Off; CK_t and CK_c: LOW; CL:
Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address,
Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in
Mode Registers2; ODT Signal: MID-LEVEL
310
mA
IDD6R
Self-Refresh Current: Reduced Temperature Range
TCASE: 0 - TBD (~35-45)°C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low; External clock: Off; CK_t and CK_c#:
LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank
Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT:
Enabled in Mode Registers2; ODT Signal: MID-LEVEL
170
mA
IDD6A
Auto Self-Refresh Current
TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4;Partial Array Self-Refresh (PASR): Full Array; CKE: Low;
External clock: Off; CK_t and CK_c#: LOW; CL: Refer to Component Datasheet for detail pattern; BL: 81; AL: 0; CS_n#, Command,
Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh operation; Output
Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL
210
mA
IDD7
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern; BL:
81; AL: CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially
toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM_n: stable at 1; Bank Activity: two
times interleaved cycling through banks (0, 1, ...7) with different addressing; Output Buffer and RTT: Enabled in Mode Registers2;
ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern
1,620
mA
IPP7
Operating Bank Interleave Read IPP Current
Same condition with IDD7
80
mA
IDD8
Maximum Power Down Current
110
mA
PDIMM
Power Consumption per DIMM
System is operating at 1200MHz clock with VDD = 1.2V. This parameter is calculated at a common loading.
2,490
mW
P1-P3P4-P6P7-P9P10-P11

96D4I-8G2400R-ATL

Mfr. #:
Buy 96D4I-8G2400R-ATL
Manufacturer:
Advantech
Description:
Memory Modules 8G DDR4 2400 1Gx8 REG VLP -40~85 SAM
Lifecycle:
New from this manufacturer.
Delivery:
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