
ADIS16400/ADIS16405
Rev. B | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THIS VIEW REPRESENTS THE TOP VIEW OF THE MATING CONNECTOR.
2. WHEN CONNECTED TO THE ADIS16400/ADIS16405, THE PINS ARE
NOT VISIBLE.
3. MATING CONNECTOR: SAMTEC CLM-112-02 OR EQUIVALENT.
4. DNC = DO NOT CONNECT.
1
DIO3
SCLK
DIN
DIO1
DIO2
VCC
GND
GND
DNC
DNC
AUX_ADC
DNC
DIO4/CLKIN
DOUT
CS
RST
VCC
VCC
GND
DNC
DNC
AUX_DAC
DNC
DNC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DIS16400/ADIS16405
TOP VIEW
(Not to Scale)
07907-005
Figure 5. Pin Configuration
-AXIS
X-AXIS
Z-AXIS
g
Y
m
Y
g
X
m
X
g
Z
m
Z
ORIGIN ALIGNMENT REFERENCE POINT
SEE MSC_CTRL[6].
NOTES
1.
a
X
,
a
Y
,
a
Z
, ARROWS INDICATE THE DIRECTION OF ACCELERATION THAT
PRODUCES A POSITIVE OUTPUT.
2.
g
X
,
g
Y
,
g
Z
, ARROWS INDICATE THE DIRECTION OF ROTATION THAT
PRODUCES A POSITIVE OUTPUT.
3.
m
X
,
m
Y
,
m
Z
, ARROWS INDICATE THE DIRECTION OF MAGNETIC FIELD THAT
PRODUCES A POSITIVE OUTPUT.
PIN 23
PIN 1
a
Y
a
X
a
Z
07907-006
Figure 6. Axial Orientation
Table 5. Pin Function Descriptions
Pin No. Mnemonic
Type
1
Description
1 DIO3 I/O Configurable Digital Input/Output.
2 DIO4/CLKIN I/O Configurable Digital Input/Output or Sync Clock Input.
16, 17, 18, 19, 22, 23, 24 DNC N/A Do Not Connect.
3 SCLK I SPI Serial Clock.
4 DOUT O SPI Data Output. Clocks output on SCLK falling edge.
5 DIN I SPI Data Input. Clocks input on SCLK rising edge.
6 CS
I SPI Chip Select.
7 DIO1 I/O Configurable Digital Input/Output.
8 RST
I Reset.
9 DIO2 I/O Configurable Digital Input/Output.
10, 11, 12 VCC S Power Supply.
13, 14, 15 GND S Power Ground.
20 AUX_DAC O Auxiliary, 12-Bit DAC Output.
21 AUX_ADC I Auxiliary, 12-Bit ADC Input.
1
S is supply, O is output, I is input, N/A is not applicable.