Ultrasensitive Hall Effect Latch
with Internally or Externally Controlled Sample and Sleep Periods
for Track Ball and Scroll Wheel Applications
A1174
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Operating Characteristics Valid over full operating voltage and ambient temperature ranges (unless otherwise specified)
Characteristic Symbol Test Conditions Min. Typ.
1
Max. Unit
Electrical Characteristics
Supply Voltage
2
V
DD
T
A
= 25°C 1.65 – 3.5 V
–40°C ≥ T
A
≥ 85°C 1.8 – 3.5 V
Output On Voltage
V
OUT(SAT)
NMOS on, I
OUT
= 1 mA – 100 300 mV
V
OUT(HIGH)
PMOS on, I
OUT
= 1 mA V
DD
– 300 V
DD
– 100 – mV
Supply Current
I
DD(EN)
Chip in awake state (enabled) – – 2.0 mA
I
DD(DIS)
Chip in sleep state (disabled) – – 8.0 μA
I
DD(AV)
Normal Clock mode, V
DD
= 2.5 V – – 71 μA
Normal Clock mode, V
DD
= 3.0 V – – 82 μA
Internal Chopper Stabilization Clock Frequency f
C
– 200 – kHz
EXTERNAL_CLK and DUAL_CLK Pins Input Current I
IN
V
EXTERNAL
_
CLK
= V
DD
, V
DUAL
_
CLK
= V
DD
– 0.5 – μA
EXTERNAL_CLK and DUAL_CLK Pins Leakage Current I
OFF
V
EXTERNAL
_
CLK
= 0 V, V
DUAL
_
CLK
= 0 V – 0.02 – μA
Supply Slew Rate
3
SR t
OFF
= 100 ms 0.1 – – V/ms
Normal Clock Mode Characteristics
4
Normal Mode Awake Duration t
awake_norm
–2546μs
Normal Mode Period t
period_norm
– 0.7 1.05 ms
External Clock Mode Characteristics
4
EXTERNAL_CLK and DUAL_CLK Pins Threshold
V
th(HIGH)
– – 0.75 × V
DD
V
V
th(LOW)
0.25 × V
DD
––V
External Clock Mode Awake Duration t
awake_ext
V
EXTERNAL_CLK
> V
th(HIGH)
46 – – μs
External Clock Mode Period t
period_ext
V
EXTERNAL_CLK
> V
th(HIGH)
80 – – μs
State Transition Delay
5
t
delay_ext
–2546μs
Dual Clock Mode Characteristics
4
Dual Clock Mode Awake Duration t
awake_dual
–2546μs
Dual Clock Mode Fast Sampling Period t
period_fast
–
8 ×
t
awake_dual
– μs
Dual Clock Mode Slow Sampling Period t
period_slow
–28–ms
Dual Clock Mode Timeout
6
t
timeout
–
100 ×
t
period_slow
–ms
Magnetic Characteristics
2
Operate Point B
OP
South pole to device branded side 5 36 55 G
Release Point B
RP
North pole to device branded side –55 –36 –5 G
Hysteresis B
HYS
B
OP
– B
RP
– 72 110 G
1
Typical values are at T
A
= 25°C and V
DD
= 2.75 V. Performance may vary for individual units, within the specified maximum and minimum limits.
2
Magnetic operate and release points vary with supply voltage.
3
If the device power supply is chopped, power-up slew rate dV
DD
/ dt has to be adjusted to ensure correct functioning of the device. t
OFF
is the time of
the power cycle when V
DD
< V
DD
(min).
4
Defined in the Functional Description section of this datasheet.
5
Time between external clock transition and resulting transition of the device between the awake and sleep states. See Functional Description section.
6
If no output transition is detected during the timeout interval, the device goes back into slow sampling. See Functional Description section.
