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72291L10PF

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19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
Figure 10. Read Timing (First Word Fall Through Mode)
WCLK
12
WEN
D
0 - D8
RCLK
tENS
REN
Q
0 - Q8
PAF
HF
PAE
IR
OR
W1 W1 W2
W3
Wm+2
W[m+3]
tOHZ
tSKEW1
tENH
tDS
tDH
tOE tA
tA
tA
tPAF
tWFF
tWFF
tENS
OE
tSKEW2
WD
4675 drw 13
tPAE
W[D-n]W[D-n-1]
tA
tA
tHF
tREF
W[D-1]
WD
tA
W[D-n+1]
W[m+4]
W[D-n+2]
(1)
(2)
tENS
D-1
][
W
D-1
][
W
NOTES:
1. t
SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of
WCLK is less than t
SKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAF. If the time between the rising edge of RCLK and the rising edge of
WCLK is less than t
SKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH.
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
20
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D – 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup
procedure. D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
5. EF goes HIGH at 60 ns + 1 RCLK cycle + tREF.
Figure 11. Retransmit Timing (IDT Standard Mode)
t
REF
t
ENH
4675 drw 14
t
A
t
ENS
W
x
WCLK
RCLK
REN
RT
EF
PAF
HF
PAE
Q
0
- Q
n
t
SKEW2
12
1
W
1
t
HF
t
PAE
t
REF
W
x+1
2
W
2
t
ENH
WEN
t
ENS
t
ENS
t
ENH
(3)
t
A
t
A
(3)
(5)
t
RTS
t
RTS
t
PAF
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D – 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
procedure. D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
SEN
SI
4675 drw16
t
ENH
t
ENS
tLDS
LD
tDS
BIT 0
EMPTY OFFSET
BIT X
BIT 0
FULL OFFSET
(1)
tENH
BIT X
(1)
tLDH
tLDHtLDH
tDH
t
REF
t
ENH
4675 drw 15
t
ENS
W
x
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q
0 - Qn
t
SKEW2
12
1
t
HF
t
PAE
t
REF
W
x+1
2
W
2
t
ENH
WEN
t
ENS
W
1
t
ENH
(4)
(5)
3
4
t
ENH
W
3
t
RTS
t
A
t
A
t
RTS
t
PAF
NOTE:
1. X = 15 for the IDT72281 and X = 16 for the IDT72291.
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72291L10PF

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Buy 72291L10PF
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Description:
IC FIFO 65536X18 LP 10NS 64QFP
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