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IDT71V416L10BEI

P1-P3P4-P6P7-P9
6.424
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
AC Test Conditions
AC Test Loads
Figure 3. Output Capacitive Derating
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
*Including jig and scope capacitance.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
Figures 1,2 and 3
3624 tbl 09
+1.5V
50
Ω
I/O
Z
0
=50
Ω
3624 drw 03
30pF
3624 drw 04
320
Ω
350
Ω
5pF*
DATA
OUT
3.3V
IDT71V416S/71V416L
1
2
3
4
5
6
7
20 40 60 80 100 120 140 160
180
200
∆t
AA,
t
ACS
(Typical, ns)
CAPACITANCE (pF)
8
3624drw 05
•
•
•
•
•
•
•
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
DC Electrical Characteristics
(1, 2, 3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD -0.2V (High).
3. Power specifications are preliminary.
4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
5. Standard power 10ns (S10) speed grade only.
Symbol
Parameter
71V416S/L10
71V416S/L12
71V416S/L15
Unit
Com'l.
Ind.
(5)
Com'l.
Ind.
Com'l.
Ind.
I
CC
Dynamic Operating Current
CS
<
V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S 200 200 180 180 170 170 mA
L 180 — 170 170 160 160
I
SB
Dynamic Standby Power Supply Current
CS >
V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(4)
S707060605050
mA
L 50 — 45 45 40 40
I
SB1
Full Standby Power Supply Current (static)
CS >
V
HC
, Outputs Open, V
DD
= Max., f = 0
(4)
S202020202020
mA
L 10 — 10 10 10 10
3624 tbl 08
Symbol
Parameter
Test Conditions
IDT71V416
Unit
Min.
Max.
|I
L
I
| Input Leakage Current V
CC
= Max., V
IN
=
V
SS
to V
DD
___
5µA
|I
LO
| Output Leakage Current V
DD
= Max., CS = V
IH
, V
OUT
= V
SS
to V
DD
___
5µA
V
OL
Output Low Voltage I
OL
= 8mA, V
DD
= Min.
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA, V
DD
= Min. 2.4
___
V
3624 tbl 07
6.42
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
5
71V416S/L10
(2 )
71V416S/L12
71V416S/L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
10
____
12
____
15
____
ns
t
AA
Address Access Time
____
10
____
12
____
15
ns
t
ACS
Chip Select Access Time
____
10
____
12
____
15
ns
t
CL Z
(1 )
Chip Select Low to Output in Low-Z
4
____
4
____
4
____
ns
t
CHZ
(1 )
Chip Select High to Output in High-Z
____
5
____
6
____
7
ns
t
OE
Output Enable Low to Output Valid
____
5
____
6
____
7
ns
t
OLZ
(1 )
Output Enable Low to Output in Low-Z
0
____
0
____
0
____
ns
t
OHZ
(1 )
Output Enable High to Output in High-Z
____
5
____
6
____
7
ns
t
OH
Output Hold from Address Change
4
____
4
____
4
____
ns
t
BE
Byte Enable Low to Output Valid
____
5
____
6
____
7
ns
t
BL Z
(1 )
Byte Enable Low to Output in Low-Z
0
____
0
____
0
____
ns
t
BHZ
(1 )
Byte Enable High to Output in High-Z
____
5
____
6
____
7
ns
WRITE CYCLE
t
WC
Write Cycle Time
10
____
12
____
15
____
ns
t
AW
Address Valid to End of Write
8
____
8
____
10
____
ns
t
CW
Chip Select Low to End of Write
8
____
8
____
10
____
ns
t
BW
Byte Enable Low to End of Write
8
____
8
____
10
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
ns
t
WR
Address Hold from End of Write
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
8
____
8
____
10
____
ns
t
DW
Data Valid to End of Write
5
____
6
____
7
____
ns
t
DH
Data Hold Time
0
____
0
____
0
____
ns
t
OW
(1 )
Write Enable High to Output in Low-Z
3
____
3
____
3
____
ns
t
WHZ
(1 )
Write Enable Low to Output in High-Z
____
6
____
7
____
7
ns
3624 tbl 10
Timing Waveform of Read Cycle No. 1
(1,2,3)
AC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. Low power 10ns (L10) speed 0ºC to +70ºC temperature range only.
DATA
OUT
ADDRESS
3624 drw 06
t
RC
t
AA
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
t
OH
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
6.426
IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
ADDRESS
OE
CS
DATA
OUT
3624 drw 07
(3)
DATA VALID
t
AA
t
RC
t
OE
t
OLZ
BHE,
BLE
(3)
t
ACS
(3)
t
BLZ
t
CLZ
(2)
t
BE
(2)
t
OH
t
OHZ
(3)
t
CHZ
(3)
t
BHZ
(3)
OUT
Timing Waveform of Read Cycle No. 2
(1)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as
short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
(1,2,4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
ADDRESS
CS
DATA
IN
3624 drw
0
(5)
(5)
(5)
DATA
IN
VALID
t
WC
t
AS
t
WHZ
(2)
t
CW
t
CHZ
t
OW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
PREVIOUS DATA VALID DATA VALID
BHE
,
BLE
t
BW
t
WP
(5)
t
BHZ
(3)
P1-P3P4-P6P7-P9

IDT71V416L10BEI

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